I am working on a project where the speed is so important.
While writing my vhdl code,
Firstly, I have used structural vhdl style where it contains some signals connecting components.The code can be synthesized but speed is low.
Secondly, I have chosen dataflow vhdl style where I used variables connecting some functions and procedures .Synthesis tool (Synplify 8.5B)says that it infers some ROMs and the code uses a lot of resources in the fpgas I targeted (Actel axcelerator ,Proasicplus families).
My questions are :
1) I am thinking that using variables(functions, procedures) makes the code faster,am I right?
2) I have read some about inferring roms (syn_romstyle attribute) etc.
Can you tell me more using this attribute?
3) How can I prevent my code using a lot of combinational resources instead of ROM blocks?
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