Is this possible: parameterizing a component structure

Hi,

I'm confused about a subject that I can't seem to find convered anywhere. Perhaps I have the wording wrong.

I have a timer component. it would be nice if I could just use the generic map, set the generic "BitWidth" to an integer, and then have the VHDL synthesizer resolve the structure. I'm aware that this can be done using behavioral code, but I tend to perfer structural design.

In other words my timer looks like this.

architecture Structure of Timer is

   component FlipFlop
      ...
   end FlipFlop;


   (some signal declarations)


begin

   FF0 : FlipFlop
      ...

   FF1 : FlipFlop
      ...

       .
       .
       .

   FF[BitWidth] : FlipFlop
      ...


   (Followed by the interconnect).

end Structure;

I'd like BitWidth (the generic integer) to be able to autogenerate (upon synthesis) the number of flipflop components used in the architecture, which includes the component instantiations as well as the number of iterations in the interconnect code. To an acceptable degree, everything I want to do would be possible using the macros in C (#if, #endif, etc).

If this is not worth the time, that's cool, but I'd like to know.

Thanks.

Norair