Running two state machines with same clock.

Hello,

I have a setup that generates a clock and valid data on each rising
edge of the clock. I tried to write the data for each clock cycle to
the RAM on the falling edge of the clock plus increments the counter on
the falling edge too.
I ran the simulator and saw that when I try to write data on the
falling edge and also increment the counter on the falling edge then I
could loose data because of close edges of the counter and clock.
Can I use the same clock to run two different state machines. One
machine will be writing the 8 bit data to a RAM on the falling edge of
the clock and the other machine will be generating the addresses or
incrementing the counter on the rising edge of the clock. Is it a good
idea or bad idea? I am also attaching the code.
Thanks
John
Process ( State_A, USB_CLK )
Begin
Case State_A is
When A0=>
inc<='0';
Data_Bus ( 13 downto <=USB_Data ( 5 downto 0 );
UBL <='0';
LBL <='0';
sec_reset <='1';
nextstate_A <=A1;
When A1 =>
inc<='0';
Data_Bus ( 7 downto 0)<= USB_Data ( 7 downto 0 );
UBL <='0';
LBL <='0';
sec_reset <='0';
nextstate_A<=A2;

When A2 =>
inc <='1';
Data_Bus ( 13 downto <= USB_Data ( 5 downto 0 );
UBL <='0';
LBL <='0';
sec_reset <='0';
nextstate_A<=A3;

When A3 =>
inc<='0';
Data_Bus ( 7 downto 0)<= USB_Data ( 7 downto 0 );
UBL <='0';
LBL <='0';
sec_reset <='0';
nextstate_A<=A2;
When others =>
nextstate_A <=A0;
End case;
End Process;
------------------------------------------------------
Process (USB_CLK, Reset)
Begin
If(Reset = '1' )Then
Indicator_LED <= '1';
State_A <= A0;
elsif (USB_CLK 'Event And USB_CLK = '0')Then
State_A <= nextstate_A;
Else
End If;
End Process;
-------------------------------------------------------
Process (USB_CLK)
Begin
If(Reset = '1' )Then
sec_counter <= ( others=>'0');
elsif (USB_CLK 'Event And USB_CLK = '1')Then
If ( inc = '1')Then
sec_counter<= sec_counter + 1;
End If;
End If;
End Process;

john

john wrote:
> Hello,
>
> I have a setup that generates a clock and valid data on each rising
> edge of the clock. I tried to write the data for each clock cycle to
> the RAM on the falling edge of the clock plus increments the counter on
> the falling edge too.
> I ran the simulator and saw that when I try to write data on the
> falling edge and also increment the counter on the falling edge then I
> could loose data because of close edges of the counter and clock.
> Can I use the same clock to run two different state machines. One
> machine will be writing the 8 bit data to a RAM on the falling edge of
> the clock and the other machine will be generating the addresses or
> incrementing the counter on the rising edge of the clock. Is it a good
> idea or bad idea? I am also attaching the code.

When you are using both the rising and falling edges of the clock you
need to treat it as if you are using clocks in two different domains.
You are also going to be susceptible to changes in duty cycle. This
doesn't necessarily make it a bad idea, but it does give you some things
to worry about when reviewing the design.

Without knowing more information about your RAM, it's a bit hard to tell
for me whether what you are trying to do is a good idea or a bad idea.
There might be a simpler way to do it.

Best regards,
Mark Norton

--
==============================
Mark Norton <>
Concept Development, Inc.
Irvine, CA, USA

Mark Norton

john wrote:

> Can I use the same clock to run two different state machines.

Yes. See case TxState_v and case RxState_v in the reference design here:
http://home.comcast.net/~mike_treseler/
for one way to do exactly that.

> One
> machine will be writing the 8 bit data to a RAM on the falling edge of
> the clock and the other machine will be generating the addresses or
> incrementing the counter on the rising edge of the clock. Is it a good
> idea or bad idea?

This is a common first step for new
designer, but it is almost always
a bad idea.

-- Mike Treseler

Mike Treseler

Hi John,
beside your problem you describe, your code has some strange lines in it:

> Process ( State_A, USB_CLK )
-- USB_CLK is not needed in the sensitivity list, but I think you want
to trick the simulator to run this process on each clock event without
writing the whole list of input signals, but then you don't need State_A
either.
> Begin
> Case State_A is

> ------------------------------------------------------
> Process (USB_CLK, Reset)
> Begin
> If(Reset = '1' )Then
> Indicator_LED <= '1';
-- The LED will never go off, will it?
> State_A <= A0;

> -------------------------------------------------------
> Process (USB_CLK)
-- You can't simulate the reset behavior without signal reset in your
sensitivity list.
> Begin


Why do you want to use both edges of the clock? I think it's not really
neccessary. when you increment your counter with the same edge as your
data is written to some (registered) device you will always see the
correct adressed data stored in your device.
But beware of writing something like

Data <= Value after time_of_clock_event;

in your testbench. This will give you a wrong simulation. Write the
assignment in a clocked process and everything is ok.

Have a nice simulation
Eilert

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