VHDL-200x and Object-Oriented Hardware design

Verilog2001 and SystemVerilog introduced the notion of a class and
objects for describing hardware and/or for verification perposes. I
have not seen any activities on the VHDL-200x-FT for adding these
features (or have I missed it?). I know of the addition of package and
subprogram generics (DTA) and also allowing composites (arrays and
records) with unconstraint arrays (FT14).

The current proposals allow for abstraction of data types and creating
more generic packages, types, functions. Any thought on the other
aspects of OO in HDL?

My question is: "Are there any proposals or work on adding
object-oriented features to VHDL?"

Seems HDLs, like the EDA tools don't catch up and go as fast as
software/compiler technologies! It's a pitty...

-- Amal

Amal

Amal wrote:

> Seems HDLs, like the EDA tools don't catch up and go as fast as
> software/compiler technologies! It's a pitty...

More's the pity that few designers
use the facilities for variables,
functions, and procedures that
already exist and work well.

-- Mike Treseler

Mike Treseler

Mike Treseler wrote:
> Amal wrote:
>
>> Seems HDLs, like the EDA tools don't catch up and go as fast as
>> software/compiler technologies! It's a pitty...
>
> More's the pity that few designers
> use the facilities for variables,
> functions, and procedures that
> already exist and work well.

Okay,okay...

I had been using procedures in testbenches for awhile, but only recently
started using them in designs at your instigation. I must say, they came
in quite handy.

Maybe it is good that you keep bugging people about it

Duane Clark

Duane Clark wrote:
> Mike Treseler wrote:
> > Amal wrote:
> >
> >> Seems HDLs, like the EDA tools don't catch up and go as fast as
> >> software/compiler technologies! It's a pitty...
> >
> > More's the pity that few designers
> > use the facilities for variables,
> > functions, and procedures that
> > already exist and work well.
>
> Okay,okay...
>
> I had been using procedures in testbenches for awhile, but only recently
> started using them in designs at your instigation. I must say, they came
> in quite handy.
>
> Maybe it is good that you keep bugging people about it

I have been using packages, procedures and functions as much as I can,
and I can see the missing features and it bothers me that we should
just be content with the language (that is a great one by the way) and
not improeve it.

I was just looking for OO proposals for VHDL-200x, anyone knows of any
proposals?

-- Amal

Amal

Amal wrote:

> I was just looking for OO proposals for VHDL-200x, anyone knows of any
> proposals?

Have a look here:

http://www.accellera.org/apps/group_...wg_abbrev=vhdl

-- Mike Treseler

Mike Treseler

The ability to create a class hierarchy in synthesizable HDL would be
nice. Seems HDLs could tame complexity and improve code re-use with
inheritance. It's a shame VHDL hasn't borrowed the notion of 'derived'
types to enable inheritance like in ADA.

Anyone know if SystemVerilog's object-orientation features are
synthesizable? If not, when?

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps

Amal wrote:
> Verilog2001 and SystemVerilog introduced the notion of a class and
> objects for describing hardware and/or for verification perposes. I
> have not seen any activities on the VHDL-200x-FT for adding these
> features (or have I missed it?). I know of the addition of package and
> subprogram generics (DTA) and also allowing composites (arrays and
> records) with unconstraint arrays (FT14).
>
> The current proposals allow for abstraction of data types and creating
> more generic packages, types, functions. Any thought on the other
> aspects of OO in HDL?
>
> My question is: "Are there any proposals or work on adding
> object-oriented features to VHDL?"
>
> Seems HDLs, like the EDA tools don't catch up and go as fast as
> software/compiler technologies! It's a pitty...
>
> -- Amal

Jeremy Ralph

"Amal" <> writes:

> Seems HDLs, like the EDA tools don't catch up and go as fast as
> software/compiler technologies! It's a pitty...
>

I wouldn't say software technologies are ahead all the time.

EG:

* There's not much in the way of tools that will tell me that my
software is guaranteed to meet my timing deadlines under all
conditions. The timing analyser guarantees my hardware will meet
timing contraints.

* Concurrency is not well handled in most widely-used software
languages. HDLs support it quite nicely.

IMHO of course!

Martin

--

TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

Martin Thompson

Surely, Brother Treseler, thou speakest the truth! Amen!

There are too many folks writing netlists in VHDL, and calling it a
VHDL design.

Andy Jones


Mike Treseler wrote:
> Amal wrote:
>
> > Seems HDLs, like the EDA tools don't catch up and go as fast as
> > software/compiler technologies! It's a pitty...
>
> More's the pity that few designers
> use the facilities for variables,
> functions, and procedures that
> already exist and work well.
>
> -- Mike Treseler

Andy

I agree and it is true that VHDL is great as it is and not everybody
writes good code or uses the features available now in VHDL. I think I
use VHDL to the extent that I feel it has many shortcomings. Some are
being addressed by Accellera, but I think OO would be a great addition
to the language.

-- Amal

Andy wrote:
> Surely, Brother Treseler, thou speakest the truth! Amen!
>
> There are too many folks writing netlists in VHDL, and calling it a
> VHDL design.
>
> Andy Jones
>
>
> Mike Treseler wrote:
> > Amal wrote:
> >
> > > Seems HDLs, like the EDA tools don't catch up and go as fast as
> > > software/compiler technologies! It's a pitty...
> >
> > More's the pity that few designers
> > use the facilities for variables,
> > functions, and procedures that
> > already exist and work well.
> >
> > -- Mike Treseler

Amal

Amal wrote:

> I think I
> use VHDL to the extent that I feel it has many shortcomings. Some are
> being addressed by Accellera, but I think OO would be a great addition
> to the language.

I agree, but I've got work to do.
The vhdl'93 revision started in 1987,
took 6 years to write and about
another 6 years to roll out into FPGA tools.

-- Mike Treseler

Mike Treseler