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8 bit binary to 2 digit BCD

 
 
Yama
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      06-05-2006
Hi all,

I have to make the following:

An 8 bit binary comes in "Parallel" May not be bigger then 99. When its
binair 23 for example I have to split it.. 1 register have to hold the
'2' and another register have to hold the '3'.
When that is done... Register1 and Register2 need to be send out
serial.

1(start bit) 3 2 1 0(Register1) 3 2 1 0 (Register2) 3 2 1 0 (Stop bit )
0

Tried to make it but cannot get it working. splitting up the binary
already go's wrong

Appreciate some help

 
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Yama
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      06-05-2006
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity BtoB is
Port ( Data_in : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Button : in STD_LOGIC;
Busy : out STD_LOGIC;
Data_uit : out STD_LOGIC;
end BtoB;

architecture Gedrag of BtoB is

shared variable Value: integer;
shared variable ValueGr: integer;
shared variable ValueKl: integer;


signal Register_1: STD_LOGIC_VECTOR(3 downto 0);
signal Register_2: STD_LOGIC_VECTOR(3 downto 0);
signal Register_3: STD_LOGIC_VECTOR(9 downto 0);

type STATE_T is (GOT0,GOT1,GOT2,GOT03,GOT4);
signal State: STATE_T;


begin

----------------------------------------------------------------------
-- Verwerk_dat_in
----------------------------------------------------------------------
Verwerk_data_in: process(Clk, Data_in,Button, Reset,Counter)

begin
if Clk ' event and Clk = '1' then
case State is
when GOT0 =>
null;
when GOT1 =>
ValueKl:= Value mod 10;
-- TempValue:= Value - ValueKl;
-- ValueGr := TempValue * (10/100);
Register_1<= conv_std_logic_vector(ValueKl, 4);
Register_2<= conv_std_logic_vector(ValueGr, 4);
Register_3 <= '1' & Register_1 & Register_2 & '0';
State <= GOT2;
when GOT2 =>
Data_uit<=Register_3(regVar);
regVar := regVar - 1;
if regVar = 0 then
State <= GOT0;
regVar := 9;
end if;
when others => State <= GOT0;
end case;
end if;
if Button = '1' then
Value:= 26;
State <= GOT1;
end if;
if Reset = '1' then

end if;
end process;

 
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Yama
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      06-05-2006
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity BtoB is
Port ( Data_in : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Button : in STD_LOGIC;
Busy : out STD_LOGIC;
Data_uit : out STD_LOGIC;
end BtoB;

architecture Gedrag of BtoB is

shared variable Value: integer;
shared variable ValueGr: integer;
shared variable ValueKl: integer;


signal Register_1: STD_LOGIC_VECTOR(3 downto 0);
signal Register_2: STD_LOGIC_VECTOR(3 downto 0);
signal Register_3: STD_LOGIC_VECTOR(9 downto 0);

type STATE_T is (GOT0,GOT1,GOT2,GOT03,GOT4);
signal State: STATE_T;


begin

----------------------------------------------------------------------
-- Verwerk_dat_in
----------------------------------------------------------------------
Verwerk_data_in: process(Clk, Data_in,Button, Reset,Counter)

begin
if Clk ' event and Clk = '1' then
case State is
when GOT0 =>
null;
when GOT1 =>
ValueKl:= Value mod 10;
-- TempValue:= Value - ValueKl;
-- ValueGr := TempValue * (10/100);
Register_1<= conv_std_logic_vector(ValueKl, 4);
Register_2<= conv_std_logic_vector(ValueGr, 4);
Register_3 <= '1' & Register_1 & Register_2 & '0';
State <= GOT2;
when GOT2 =>
Data_uit<=Register_3(regVar);
regVar := regVar - 1;
if regVar = 0 then
State <= GOT0;
regVar := 9;
end if;
when others => State <= GOT0;
end case;
end if;
if Button = '1' then
Value:= 26;
State <= GOT1;
end if;
if Reset = '1' then

end if;
end process;

 
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Dave Pollum
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      06-09-2006
Yama wrote:
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> use IEEE.NUMERIC_STD.ALL;
>
> entity BtoB is
> Port ( Data_in : in STD_LOGIC_VECTOR (7 downto 0);
> Clk : in STD_LOGIC;
> Reset : in STD_LOGIC;
> Button : in STD_LOGIC;
> Busy : out STD_LOGIC;
> Data_uit : out STD_LOGIC;
> end BtoB;
>
> architecture Gedrag of BtoB is
>
> shared variable Value: integer;
> shared variable ValueGr: integer;
> shared variable ValueKl: integer;
>
>
> signal Register_1: STD_LOGIC_VECTOR(3 downto 0);
> signal Register_2: STD_LOGIC_VECTOR(3 downto 0);
> signal Register_3: STD_LOGIC_VECTOR(9 downto 0);
>
> type STATE_T is (GOT0,GOT1,GOT2,GOT03,GOT4);
> signal State: STATE_T;
>
>
> begin
>
> ----------------------------------------------------------------------
> -- Verwerk_dat_in
> ----------------------------------------------------------------------
> Verwerk_data_in: process(Clk, Data_in,Button, Reset,Counter)
>
> begin
> if Clk ' event and Clk = '1' then
> case State is
> when GOT0 =>
> null;
> when GOT1 =>
> ValueKl:= Value mod 10;
> -- TempValue:= Value - ValueKl;
> -- ValueGr := TempValue * (10/100);
> Register_1<= conv_std_logic_vector(ValueKl, 4);
> Register_2<= conv_std_logic_vector(ValueGr, 4);
> Register_3 <= '1' & Register_1 & Register_2 & '0';
> State <= GOT2;
> when GOT2 =>
> Data_uit<=Register_3(regVar);
> regVar := regVar - 1;
> if regVar = 0 then
> State <= GOT0;
> regVar := 9;
> end if;
> when others => State <= GOT0;
> end case;
> end if;
> if Button = '1' then
> Value:= 26;
> State <= GOT1;
> end if;
> if Reset = '1' then
>
> end if;
> end process;


To find out how to convert binary to decimal, do a search in this
newsgroup for "binary to decimal" or "binary to BCD". Also, it's best
to only use the libraries: STD_LOGIC_1164 and NUMERIC_STD, and to not
use STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED.
BTW, what happens when Reset is '1'? Usually the starting state is
assigned, for example:

if Reset = '1' then
State <= GOT0;
elsif rising_edge( clk ) then
case State is
...
end case;
end if;

 
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