common dataflow tree for verilog and vhdl

Hi,

I am trying to write a tool that shall process synthesizable HDL. I
wish to do this in a way such that I can support both Verilog and VHDL
without too much extra effort. (I don't really care about the
simulation specific syntactic structures of the languages, the
synthesizable subset is good enough.)

Does anybody know of any good open-source parsers for verilog and vhdl
that produce a common dataflow tree, that I might use as my starting
point?

Thanks.
Nikhil

Nikhil Patil

Nikhil,
I'm not EDA tool developer so am not sure of a common data model,
however Icarus Verilog has a synthesis engine and is open source. See
www.icarus.com/iverilog. GHDL is a GNU VHDL compiler/simulator, open
source. CVER is another popular open source Verilog simulator.

HTH
Ajeetha, CVC
www.noveldv.com
Nikhil Patil wrote:
> Hi,
>
> I am trying to write a tool that shall process synthesizable HDL. I
> wish to do this in a way such that I can support both Verilog and VHDL
> without too much extra effort. (I don't really care about the
> simulation specific syntactic structures of the languages, the
> synthesizable subset is good enough.)
>
> Does anybody know of any good open-source parsers for verilog and vhdl
> that produce a common dataflow tree, that I might use as my starting
> point?
>
> Thanks.
> Nikhil

Ajeetha