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VHDL - fsm

 
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Old 05-26-2006, 08:34 PM   #1
Default fsm


http://pastebot.perl.it/cgi-bin/Past...owpaste;id=542

this is my fsm, it works!
but i think it's a bit verbose, don't u think?

there's a way to make it shortly?




Gandalf
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Old 05-28-2006, 12:07 PM   #2
Nicolas Matringe
 
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Default Re: fsm
Gandalf a écrit :
> http://pastebot.perl.it/cgi-bin/Past...owpaste;id=542
>
> this is my fsm, it works!
> but i think it's a bit verbose, don't u think?
>
> there's a way to make it shortly?



Hi
I've just had a *very* quick look at it.
Are you sure you need that many states? Can't you use a counter in some
states instead of a long sequence?

Use ieee.numeric_std instead of ieee.std_logic_arith and
ieee.std_logic_unsigned (there is a recent thread in this newsgroup
about why you should)

Nicolas


Nicolas Matringe
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Old 05-28-2006, 02:36 PM   #3
Gandalf
 
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Default Re: fsm
i tryed to re-write the code to make it more shortly and i have this:
http://pastebot.perl.it/cgi-bin/Past...owpaste;id=547

i used the libreries u told me.

this is a simulation with ModelSim:
http://www.geocities.com/bagbyte/simulation.jpg

how u can see, there is a small time in which the counter conta_rom change
it's value 2 time so my FSM soesn't work how it could work!

can u tell me why i have this result?

this simulation is for the sates from s0 to s14.




Gandalf
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