Marco wrote:
> do you mean that if I set a default value in the declaration part,
> while I forget to specify a value in the instantiation, I'll synthesize
> with the inserted default value and I'll have a testbeanch with another
> one, different from the default one?
If you have a component as in your example
component <component_name>
generic (
my_generic : integer := 1;
<other generics>...
);
port (
<port_name> : <mode> <type>;
<other ports>...
);
end component;
and you synthesize this component alone without giving a different
actual value to the generic my_generic, the synthesis tool will
synthesize with the default value which is 1.
Now, if you simulate your netlist inside your design making an
instantiation as in your example
Component Instantiation:
<instance_name> : <component_name>
generic map (
my_generic => 2,
<other generics>...
)
port map (
<port_name> => <signal_name>,
<other ports>...
);
then this will lead to wrong behavior, because the instantiation assumes
my_generic to be 2, but the netlist was synthesized with my_generic=1.
The netlist is fixed.
This pitfall is not a special behavior, but simply something, that can
be easily forgotten.
Ralf
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