dilou wrote:

> I need your help for implementing the pwl in FPGA using VHDL. In a

> study I have found this approximation of the sigmoid function:

>

> It can be approximate it at:

> y(v) = mi( v-vi-1) + ni-1 , v <> [ vi-1, vi]

> ni = mi ( vi - vi-1 ) + ni-1, i=1,2,3,...

> with v0=0, n0=0

>

>

>

> i : number of sections of the interval of (v) of the function

> yi : linear approximation of the function in the section i

> mi : slope in the section i

> ni : ordered in the origin of section i

>

>

>

> It said that the hardware for implementing this version is:

> · comparators to determinate the area,

> · multipliers,

> · the sumator and a set of registers to save the differents valors

> of slope and displacement and the mi and ni.

>

> My problem is:

>

> I don't know how can I choose the slope and the interval, also if

> this method is best or no?

> Mu project is to implement a Hopfield network with the pwl function

> instead of the look up table function.
I think you should look at my other reply. A sequence of the sort:

if (value >= v0 and value < v1) then

-- Use region v0 to v1 slope and intercept to calculate

elsif (value >= v1 and value < v2) then

-- Use region v1 to v2 slope and intercept

elsif (...

-- Last region

end if;

will generate comparators to check "value" against the v0, v1, ... vn

numbers and the sections in between you will multiply and add numbers to

get to the output. As far as I can tell, that will generate

comparators, multipliers, and a summation structures.

Apart from this, I don't know what more to tell you. If the syntax

looks unfamiliar, I would advise cracking open a book on VHDL.

Best regards,

Mark Norton

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==============================

Mark Norton <(E-Mail Removed)>

Concept Development, Inc.

http://www.cdvinc.com