Velocity Reviews > VHDL > frequency divider

# frequency divider

Gandalf
Guest
Posts: n/a

 05-20-2006
Hi,
i need a frequency divider for the clock.
The Virtex fpga has a clock of 50MHz i need a clock of 1MHz.
can somebody help me?

some VHDL script?

thank u

Ralf Hildebrandt
Guest
Posts: n/a

 05-21-2006
Gandalf wrote:

> The Virtex fpga has a clock of 50MHz i need a clock of 1MHz.

What about the obvious divide-by-50 - counter? (Count to 25, invert output.)

Maybe your FPGA offers a specialized frequency divider.

Note, that the divided clock should be routed via a global clock net.

Ralf

Gandalf
Guest
Posts: n/a

 05-21-2006
i'm don't know the "obvious divide-by-50 - counter"

can u write me the code please?

Ralf Hildebrandt
Guest
Posts: n/a

 05-21-2006
Gandalf wrote:
> i'm don't know the "obvious divide-by-50 - counter"

Count with every rising edge of your input clock till 25, then invert a
flipflop. Do it infinitely. Remember, that your output flipflop has to
be reseted.

I strongly suggest reading a VHDL book. This is a very basic task. If
you can't solve it, you will have serious problems with more complex tasks.

Ralf

Gandalf
Guest
Posts: n/a

 05-21-2006
architecture divisore_body of divisore is
signal count: integer range 0 to 50;

begin
process(clk_in)

begin

if rising_edge(clk_in) then
if (count<25) then
clk_out <= '1';
count<= count+1;
elsif (count>=25 and count<50) then
clk_out<='0';
count <= count+ 1;
elsif (count=50) then
clk_out<='1';
count<=1;
end if;
end if;

end process;
end divisore_body

---------------------------------

what do u think?

Ralf Hildebrandt
Guest
Posts: n/a

 05-21-2006
Gandalf wrote:

> architecture divisore_body of divisore is
> signal count: integer range 0 to 50;
>
> begin
> process(clk_in)
>
> begin
>
> if rising_edge(clk_in) then
> if (count<25) then
> clk_out <= '1';
> count<= count+1;
> elsif (count>=25 and count<50) then
> clk_out<='0';
> count <= count+ 1;
> elsif (count=50) then
> clk_out<='1';
> count<=1;
> end if;
> end if;
>
> end process;
> end divisore_body
>
> ---------------------------------
>
> what do u think?

Too much overhead but the right idea. You forgot a reset.

process(reset,clk)
begin
if (reset='0') then
count<=0;
clk_out<='0';
elsif rising_edge(clk) then
if (count=24) then -- 0 to 24 = 25 clocks
clk_out<=NOT(clk_out);
count<=0;
else
count<=count+1;
end if;
end if;
end process;

Note that you should feed clk_out via global nets. Otherwise you will
have a lot of clock skew.
Note also, that your FPGA may provide special components for frequency
synthesis / division.

Ralf

solrac215
Junior Member
Join Date: Sep 2008
Posts: 1

 09-24-2008
this is my current code, that divides 100MHz to 10Mhz, i'm finding it hard to recode it in such a way that it will produce 20Mhz.

can anyone help me out?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- This clock divider circuit outputs a frequency equal to 100MHz?

entity freqdiv is
Port ( clk_in : in std_logic;
res : in std_logic;
div10out : out std_logic);
end freqdiv;

architecture Behavioral of freqdiv is
component div10
Port ( clk : in std_logic;
res : in std_logic;
div2out : out std_logic);
end component;

begin

u1: div10 port map (clk_in,res,div10out); --10MHz

end Behavioral;

--subcomponent responsible for frequency division/counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div10 is
Port ( clk : in std_logic;
res : in std_logic;
div2out : out std_logic);
end div10;

architecture Behavioral of div10 is
signal cntr : std_logic_vector (3 downto 0);
begin
process (clk, res)
begin

if res = '1' then
cntr <= "0000";
div2out <= '0';
else

if clk'event and clk = '0' and res ='0' then
cntr <= cntr + 1;
if cntr = "0100" then
div2out <= '1';
end if;
if cntr = "1001" then
div2out <= '0';
cntr <= "0000";
end if;

end if;
end if;
end process;

end Behavioral;