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Std_Logic signal assignment snafu

Norair Norair is offline
Junior Member
Join Date: May 2006
Location: Melbourne, FL
Posts: 2
As you can tell, I'm new to VHDL. I have tried searching this forum, but the search tool either doesn't work or I have come up short.

I am using the downloadable Xilinx ISE. I have this line of code, for example:

RXSize(3 downto 0) <= B"0001";

RXSize is a 4bit long std_logic_vector SIGNAL. I know that I must be doing something wrong with the types, but I can't for the life of me figure it out since the same nomenclature (i.e. B"XXXX") seems to work declaring for the initial values.

This is irritating, because I have a fair amount of logic design experience and would like to get on with the project!
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