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For a small project, I'll be using a 16x4 RAM, as I'm using Xilinx
tools, I decided to try the Core Generator for creating this memory.

As testbench waveforms are not supported for units created using the
CoreGen, I created a top VHDL source to test the memory, this is the
code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top_memory is
Port ( clk : in  STD_LOGIC;
read: in  STD_LOGIC;
address: in  STD_LOGIC_VECTOR (3 downto 0);
input: in  STD_LOGIC_VECTOR (3 downto 0);
output: out  STD_LOGIC_VECTOR (3 downto 0));
end top_memory;

architecture Behavioral of top_memory is

-- The following code must appear in the VHDL architecture header:

component memory
port (
addr: IN std_logic_VECTOR(3 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(3 downto 0);
dout: OUT std_logic_VECTOR(3 downto 0);
we: IN std_logic);
end component;

begin

instance: memory
port map (
addr => address,
clk => clk,
din => input,
dout => output,
we => read);

end Behavioral;

Next, I create a testbench wavefor for this top VHDL file, but I can't
get its simulation, because when calling "Generate Expected Simulation
Results" I always get this message:

ERROR: VSim failed to simulate annotated testbench

This is the full output to the console:

Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl

# 6.0a

# do top_memory_tb.ado
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
2004
# -- Compiling module memory
#
# Top level modules:
#    memory
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10
2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity top_memory
# -- Compiling architecture behavioral of top_memory
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10
2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity top_memory_tb
# -- Compiling architecture testbench_arch of top_memory_tb
# Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
2004
# -- Compiling module glbl
#
# Top level modules:
#    glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps
top_memory_tb glbl
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading work.top_memory_tb(testbench_arch)
# ** Warning: (vsim-3479) Time unit 'fs' is less than the simulator
resolution (1ps).
#    Time: 0 ps  Iteration: 0  Region: /
# XE version supports only a single HDL -- <= I think this is
the problem
# Error loading design
Error loading design
ERROR: VSim failed to simulate annotated testbench

I think this line is the problem:

# XE version supports only a single HDL

However, I must comment that the simulation worked once but it doesn't
work anymore (I always get that error message).

Also, what do these lines mean?

# Top level modules:
# glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps
top_memory_tb glbl

I have a doubt, why it tryes to compile two sources when calling the
compiler? Does anybody know what's that glbl?

Does anybody know how ISE Webpack 8.1 calls Modelsim?

Thanks in advance for your help,
José J. Enríquez.

Well, I guess the problem is that Webpack 8.1 is creating that call to
the glbl top level module, I don't know why it does so since the
previous version of ISE doesn't make any call to that module.

This is the Foundation 7.1 console output, I'm using Modelsim 6.0d, the
one I downloaded from Xilinx, not the one included in the 7.1 software
package (6.0a).

-----------------------------------------------------------------------------------------
Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl

# 6.0d

# do top_memory_tb.ado
listening on address 127.0.0.1 port 1200
# resume
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26
2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity memory
# -- Compiling architecture memory_a of memory
# -- Loading package textio
# -- Loading package ul_utils
# -- Loading package mem_init_file_pack_v6_1
# -- Loading package iputils_conv
# -- Loading package blkmemsp_pkg_v6_1
# -- Loading entity blkmemsp_v6_1
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26
2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity top_memory
# -- Compiling architecture behavioral of top_memory
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005.04 Apr 26
2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity top_memory_tb
# -- Compiling architecture testbench_arch of top_memory_tb
# vsim -lib work -t 1ps top_memory_tb
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading work.top_memory_tb(testbench_arch)
# ** Warning: (vsim-3479) Time unit 'fs' is less than the simulator
resolution (1ps).
# Time: 0 ps Iteration: 0 Region: /
# Loading work.top_memory(behavioral)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/xilinxcorelib.ul_utils(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/xilinxcorelib.mem_init_file_pack_v6_1(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/xilinxcorelib.iputils_conv(body)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/xilinxcorelib.blkmemsp_pkg_v6_1(body)
# Loading work.memory(memory_a)
# Loading
C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/xilinxcorelib.blkmemsp_v6_1(behavioral)
# ** Failure: Success! Simulation for annotation completed
# Time: 2100 ns Iteration: 0 Process: /top_memory_tb/line__105
File: top_memory_tb.ant
# Break at top_memory_tb.ant line 175
# Stopped at top_memory_tb.ant line 175


Compiling vhdl file "d:/programs/vhdl/memory/top_memory.vhd" in Library
work.
Entity <top_memory> compiled.
Entity <top_memory> (Architecture <Behavioral>) compiled.
-----------------------------------------------------------------------------------------

As it can be seen, the call to Modelsim is just

# vsim -lib work -t 1ps top_memory_tb

and not

vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps
top_memory_tb glbl

as Webpack 8.1 did.

I'd like to know how or where Webpack 8.1 stores the commands for
calling Modelsim, I've seen something about custom do file in the
"Generate Expected Simulation Results" properties, but didn't find any
..do file within project directory.

I've decided to work at school with Foundation (not Webpack) version
7.1 (the ISE Webpack suite included in the Starter Kit board I bought
from Xilinx does not include the Core Generator, well, it's there but
not all the options), it's just that I don't have enough time for
testing and making version 8.1 to work properly nor to design in ISE
and compile separately in Modelsim .

Thanks for any advice/comment you may have.

Regards,
José Jorge Enríquez.

[aubepart]

Hello,

I have the simulary error when I simulate a description with more 2 HDL files.
I work with ISE 8.1 (full version) and ModelSim 6.0a or 6.0d version.

F. Aubépart

[randompost7]

ISE8 is weird about "generated Simulated Language", which is not a feature in ISE8 but was in ISE7. However, you can specify on each module what target language to use. For me, Verilog was the default language.

To fix:
1) Click the Sources Tab. Make sure the "Source For:" is sent to "synthesis/Implementation".
2) Select a module.
3) In the Processes box below, click the plus sign next to "Design Utilities".
4) Right click "View HDL Instantiation Template" and select properties
5) Change the value to VHDL or Verilog depending on the language. (NOTE: If using the free version of Modelsim, make sure it is set to the one language Modelsim is set to use). Click "OK".
6) Repeat steps 2-5 for each module in the design

This removed my error message. Hope it helps ya.
ENJOY!
-TMM