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Verification by Non-HDL(C++/Java)??

 
 
Davy
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      05-10-2006
Hi all,

I found that some verification procedure using Non-HDL such as
C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also
generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy

 
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naren
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      05-10-2006

Davy wrote:

> Hi all,
>
> I found that some verification procedure using Non-HDL such as
> C++/Java.
>
> But how these Non-HDL language generate edge stimulus? Can Non-HDL also
> generate @posedage???
>
> Is there any basic idea behind it?
>
> Best regards,
> Davy


Hi Davy,
They do it through an interface called VHPI (for VHDL) or PLI (for
verilog). A quick googling should give you decent links.
You could also write t/b's in perl / python et.al...
Thanks,
Naren.

 
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Hans
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      05-10-2006
and you might also want to look at SystemC which, IMHO, is easier to
interface to Verilog/VHDL.

Hans
www.ht-lab.com


"naren" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
>
> Davy wrote:
>
>> Hi all,
>>
>> I found that some verification procedure using Non-HDL such as
>> C++/Java.
>>
>> But how these Non-HDL language generate edge stimulus? Can Non-HDL also
>> generate @posedage???
>>
>> Is there any basic idea behind it?
>>
>> Best regards,
>> Davy

>
> Hi Davy,
> They do it through an interface called VHPI (for VHDL) or PLI (for
> verilog). A quick googling should give you decent links.
> You could also write t/b's in perl / python et.al...
> Thanks,
> Naren.
>



 
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Srinivasan Venkataramanan
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      05-11-2006
Davy,
Try http://teal.sf.net

Though I would rather use SystemVerilog for the same.

Good Luck
Ajeetha, CVC
www.noveldv.com

 
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mmintz@gmail.com
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      05-11-2006
Hi Davy,

I am the creator to teal. Let me know if I can help in any way.

I am also real close to releasing a verification framework in C++.

Take Care,
Mike

 
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