I need help for RAM coding In verilog

I wand document and and idea for ram coding and verification with
timing cycles included.
plz send it in verilog.

apssingh

Hi,
Why not ask for that in comp.lang.verilog then? Also, a simple RAM
will be:

reg [31:0] ram [7:0];

Timing etc. - why not refer to a standard data sheet?

Ajeetha
www.noveldv.com

Ajeetha