FPGA interface design to access the BRAM

Hi guys:

Currently I am try to design a interface between PPC, FPGA and BRAM.
Because it is my first time working on the FPGA design, can anyone give
me some idea about how to design the interface between BRAM and FPGA?
In my the design, FPGA needs to access the shared BRAM (share with PPC)
and read the data from a memory address and write the data back to the
BRAM once it finishes.






WilliamS

pingluns@gmail.com