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VHDL - Help! FIR Filter - MATLAB fdatool - VHDL |
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Hi,
I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that in the following part of the code there is a problem (Delay pipe line is an 8 element array, whose elements are 16 bit vectors. filter_in is a 16 bit vector): IF reset = '1' THEN delay_pipeline(0 TO 7) <= (OTHERS => (OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0) <= signed(filter_in); delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); END IF; END IF; This part simply shifts previous inputs and should be saving the new input (filter_in) into delay_pipeline(0) (which it does). However, after delay_pipeline(0) <= signed(filter_in);, it says delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);. As far as I know, the statements in a process are sequential. So, if you change delay_pipeline(0) right at the beginning, isn't the old value of delay_pipeline(0) totally gone? Because, afterwards delay_pipeline(0) (its new value) is assigned to delay_pipeline(1). I think that the order of the statements needs to be changed like: delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); delay_pipeline(0) <= signed(filter_in); so that the seven previous inputs are stored in the array elements with indices from 1 to 7 and the new(current) input is stored in the element with index 0. I couldn't be sure. Can anyone help me? It is very crucial to me that I understand it correctly. Thanks in advance... Emel Emel |
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