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VHDL - Asynch. signal

 
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Old 01-06-2006, 10:13 PM   #1
Default Asynch. signal


Hi,

I have interfaced the eight bit data bus and the clock signal of the
USB device to the CPLD. The USB device stores 8 bit in the CPLD'S
buffer at every clcok cycle . I need to store 32 bits in the buffer
then serial out those bits. I can not serial out the data on the USB
clock because when there is not data there is no clock thats how the
USB device works. So, I planned to have another clock which serial out
the data. But I am worried about the communication between the the two
processes. Because when the buffer is full, it will generate the signal
to the serial out process and that Flag signal might be missed. So can
somebody advice me with a solution.

Thanks
Regards
John



john
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