how to initialize 2 BRAM (RAMB16_S18)

dear

I am trying to initialize 1024 numbers (each 32 bit) in one entity,
using XIilinx BRAM.

In VHDL, BRAM (RAMB16_S18, 1024-deep, 16-wide) have been declared and
instantiated as shown below.

Problem is that I do not know how to initialize (for example, using
'generic' and 'INIT_XX') BRAM, in case there is ONE declaration and TWO
instantiations of identical component.

Does someone have experience?

Thankyou in advance, regards

------------------------------------------------------------------------------------------------------
-- declare BRAM RAMB16_S18
component RAMB16_S18
port (
DO: out STD_LOGIC_VECTOR (15 downto 0;
DOP: out STD_LOGIC_VECTOR (1 downto 0);
ADDR: in STD_LOGIC_VECTOR (9 downto 0);
CLK: in STD_ULOGIC;
DI: in STD_LOGIC_VECTOR (15 downto 0);
DIP: in STD_LOGIC_VECTOR (1 downto 0);
EN: in STD_ULOGIC;
SSR: in STD_ULOGIC;
WE: in STD_ULOGIC);
end component;
..
..
--Instantiation of BRAM 1
RAM00 : RAMB16_S18
port map(
do => doMem(15 downto 0),
dop => dop1,
addr => addrMem,
clk => clock,
di => diMem(15 downto 0),
dip => dip1,
en => enMem,
ssr => reset,
we => weMem);

--Instantiation of BRAM 2
RAM01 : RAMB16_S18
port map(
do => doMem(31 downto 16),
dop => dop2,
addr => addrMem,
clk => clock,
di => diMem(31 downto 16),
dip => dip2,
en => enMem,
ssr => reset,
we => weMem);
---------------------------------------------------------------------------------------------

Pasacco

Hi, on page 174 of the XST User Guide you'll find what you need, here's
an extract:

....
type ram_type is array (0 to 63) of std_logic_vector(19 downto 0);
signal RAM : ram_type :=
(
X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");
....
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(conv_integer(a)) <= di;
end if;
ra <= a;
end if;
end process;
....
do <= RAM(conv_integer(ra));

Marco

Marco

Hi,

I tried the initialization as shown below....but not yet working --:

Wondering why....

thankyou for reference...

------------------------------------------------------------------------------------------
-- declare BRAM RAMB16_S18
component RAMB16_S18
port (
DO: out STD_LOGIC_VECTOR (15 downto 0);
DOP: out STD_LOGIC_VECTOR (1 downto 0);
ADDR: in STD_LOGIC_VECTOR (9 downto 0);
CLK: in STD_ULOGIC;
DI: in STD_LOGIC_VECTOR (15 downto 0);
DIP: in STD_LOGIC_VECTOR (1 downto 0);
EN: in STD_ULOGIC;
SSR: in STD_ULOGIC;
WE: in STD_ULOGIC);
end component;

attribute INIT: string;
attribute INIT_00: string;
attribute INIT_01: string;
attribute INIT_02: string;
attribute INIT_03: string;
attribute INIT_04: string;
attribute INIT_05: string;
attribute INIT_06: string;
attribute INIT_07: string;
attribute INIT_08: string;
attribute INIT_09: string;
attribute INIT_0a: string;
attribute INIT_0b: string;
attribute INIT_0c: string;
attribute INIT_0d: string;
attribute INIT_0e: string;
attribute INIT_0f: string;

-- first bram : RAM0 : Data[15:0]
attribute INIT_00 of RAM0: label is
"000000E30000001A00000051000000C500000014000000C30 00000A200000034";
attribute INIT_01 of RAM0: label is
"000000E40000002A00000041000000C50000002D000000C30 000005200000045";
attribute INIT_02 of RAM0: label is
"000000E10000003A00000031000000C50000003D000000C30 0000057000000C6";
attribute INIT_03 of RAM0: label is
"000000A70000006A00000021000000C50000004D000000C30 000005300000067";
attribute INIT_04 of RAM0: label is
"000000A60000005A00000011000000C50000005D000000C30 000006200000020";
attribute INIT_05 of RAM0: label is
"000000A50000004A00000026000000C500000062000000C30 00000820000005F";
attribute INIT_06 of RAM0: label is
"000000B40000009A00000036000000C500000074000000C30 0000072000000C8";
attribute INIT_07 of RAM0: label is
"000000B30000008A00000046000000C500000084000000C30 0000069000000D7";
attribute INIT_08 of RAM0: label is
"000000B20000007A00000056000000C500000099000000C30 000005200000018";
attribute INIT_09 of RAM0: label is
"000000D10000006D00000066000000C5000000A8000000C30 000004200000077";
attribute INIT_0a of RAM0: label is
"000000D90000005D00000076000000C5000000B4000000C30 0000032000000C6";
attribute INIT_0b of RAM0: label is
"000000DF0000004D00000086000000C5000000C4000000C30 000008200000063";
attribute INIT_0c of RAM0: label is
"000000EA0000003F00000096000000C5000000D6000000C30 0000063000000A4";
attribute INIT_0d of RAM0: label is
"000000EE0000002E000000A6000000C5000000E2000000C30 0000012000000A2";
attribute INIT_0e of RAM0: label is
"0000001D0000001E000000D6000000C5000000F1000000C30 0000012000000C7";
attribute INIT_0f of RAM0: label is
"0000001F0000007E000000F6000000C5000000C2000000C30 000002E000000C1";


-- second bram : RAM1 : Data[31:16]
attribute INIT_00 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_01 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_02 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_03 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_04 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_05 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_06 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_07 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_08 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_09 of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_0a of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_0b of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_0c of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_0d of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_0e of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
attribute INIT_0f of RAM1: label is
"0000000000000000000000000000000000000000000000000 000000000000000";
..
..
..
--Instantiation of RAM 0
RAM0 : RAMB16_S18
port map(
do => dout(15 downto 0),
dop => dop1,
addr => addr,
clk => clock,
di => din(15 downto 0),
dip => dip1,
en => en,
ssr => reset,
we => we);

--Instantiation of RAM 1
RAM1 : RAMB16_S18
port map(
do => dout(31 downto 16),
dop => dop2,
addr => addr,
clk => clock,
di => din(31 downto 16),
dip => dip2,
en => en,
ssr => reset,
we => we);
-----------------------------------------------------------------------------------

Pasacco

Hi, I don't know if you could pass as a string attribute a hex value.
Could it be the fault?

Marco

Well, the attributes are passed to synthesis tools and they will be
annotated into your netlist. If you want to be able to simulate with
those initial values you need to pass those same values as generics to
the RAM model.

-- Amal

Pasacco wrote:
> Hi,
>
> I tried the initialization as shown below....but not yet working --:
>
> Wondering why....
>
> thankyou for reference...
>
> ------------------------------------------------------------------------------------------
> -- declare BRAM RAMB16_S18
> component RAMB16_S18
> port (
> DO: out STD_LOGIC_VECTOR (15 downto 0);
> DOP: out STD_LOGIC_VECTOR (1 downto 0);
> ADDR: in STD_LOGIC_VECTOR (9 downto 0);
> CLK: in STD_ULOGIC;
> DI: in STD_LOGIC_VECTOR (15 downto 0);
> DIP: in STD_LOGIC_VECTOR (1 downto 0);
> EN: in STD_ULOGIC;
> SSR: in STD_ULOGIC;
> WE: in STD_ULOGIC);
> end component;
>
> attribute INIT: string;
> attribute INIT_00: string;
> attribute INIT_01: string;
> attribute INIT_02: string;
> attribute INIT_03: string;
> attribute INIT_04: string;
> attribute INIT_05: string;
> attribute INIT_06: string;
> attribute INIT_07: string;
> attribute INIT_08: string;
> attribute INIT_09: string;
> attribute INIT_0a: string;
> attribute INIT_0b: string;
> attribute INIT_0c: string;
> attribute INIT_0d: string;
> attribute INIT_0e: string;
> attribute INIT_0f: string;
>
> -- first bram : RAM0 : Data[15:0]
> attribute INIT_00 of RAM0: label is
> "000000E30000001A00000051000000C500000014000000C30 00000A200000034";
> attribute INIT_01 of RAM0: label is
> "000000E40000002A00000041000000C50000002D000000C30 000005200000045";
> attribute INIT_02 of RAM0: label is
> "000000E10000003A00000031000000C50000003D000000C30 0000057000000C6";
> attribute INIT_03 of RAM0: label is
> "000000A70000006A00000021000000C50000004D000000C30 000005300000067";
> attribute INIT_04 of RAM0: label is
> "000000A60000005A00000011000000C50000005D000000C30 000006200000020";
> attribute INIT_05 of RAM0: label is
> "000000A50000004A00000026000000C500000062000000C30 00000820000005F";
> attribute INIT_06 of RAM0: label is
> "000000B40000009A00000036000000C500000074000000C30 0000072000000C8";
> attribute INIT_07 of RAM0: label is
> "000000B30000008A00000046000000C500000084000000C30 0000069000000D7";
> attribute INIT_08 of RAM0: label is
> "000000B20000007A00000056000000C500000099000000C30 000005200000018";
> attribute INIT_09 of RAM0: label is
> "000000D10000006D00000066000000C5000000A8000000C30 000004200000077";
> attribute INIT_0a of RAM0: label is
> "000000D90000005D00000076000000C5000000B4000000C30 0000032000000C6";
> attribute INIT_0b of RAM0: label is
> "000000DF0000004D00000086000000C5000000C4000000C30 000008200000063";
> attribute INIT_0c of RAM0: label is
> "000000EA0000003F00000096000000C5000000D6000000C30 0000063000000A4";
> attribute INIT_0d of RAM0: label is
> "000000EE0000002E000000A6000000C5000000E2000000C30 0000012000000A2";
> attribute INIT_0e of RAM0: label is
> "0000001D0000001E000000D6000000C5000000F1000000C30 0000012000000C7";
> attribute INIT_0f of RAM0: label is
> "0000001F0000007E000000F6000000C5000000C2000000C30 000002E000000C1";
>
>
> -- second bram : RAM1 : Data[31:16]
> attribute INIT_00 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_01 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_02 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_03 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_04 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_05 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_06 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_07 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_08 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_09 of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_0a of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_0b of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_0c of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_0d of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_0e of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> attribute INIT_0f of RAM1: label is
> "0000000000000000000000000000000000000000000000000 000000000000000";
> .
> .
> .
> --Instantiation of RAM 0
> RAM0 : RAMB16_S18
> port map(
> do => dout(15 downto 0),
> dop => dop1,
> addr => addr,
> clk => clock,
> di => din(15 downto 0),
> dip => dip1,
> en => en,
> ssr => reset,
> we => we);
>
> --Instantiation of RAM 1
> RAM1 : RAMB16_S18
> port map(
> do => dout(31 downto 16),
> dop => dop2,
> addr => addr,
> clk => clock,
> di => din(31 downto 16),
> dip => dip2,
> en => en,
> ssr => reset,
> we => we);
> -----------------------------------------------------------------------------------

Amal

Hi,
Pasacco schrieb:
> Problem is that I do not know how to initialize (for example, using
> 'generic' and 'INIT_XX') BRAM, in case there is ONE declaration and TWO
> instantiations of identical component.
>
> Does someone have experience?

I use the way described in xst.pdf (page 176, 177) which should come
along with your tools and extended it by using the name of the file to
initialise the RAM as Generic

ENTITY ram IS
GENERIC( RamInitFile : String := "raminitfile.data" );
PORT( .....);

The actual used filename is then configured in the configuration of the
modul containing the different instances of the RAM.

The way using the init-ram-function is synthesisable with xst and
should work fine with every simulation tool.

bye Thomas

Thomas Stanka