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VHDL - eliminate concurrent statement |
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#1 |
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Hi,
I would like to do something like : if a < b then c <= '1'; else c <= '0'; end fi; where a and b are SIGNED vectors and c is std_logic. I get the warning "Illegal concurrent statement" because it is not embedded inside a process block. I don't really need the if then else structure to implement what I want. Basically, I just want the bit corresponding to the sign of a-b to be connected to c. How can I do this without the if then else statement so that I don't get the "Illegal concurrent statement" warning. Thanks. PS : I am a beginner. Aji |
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#2 |
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Posts: n/a
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Aji wrote: > Hi, > > I would like to do something like : > > if a < b then c <= '1'; else c <= '0'; end fi; > > where a and b are SIGNED vectors and c is std_logic. > > I get the warning "Illegal concurrent statement" because it is not embedded > inside a process block. > > I don't really need the if then else structure to implement what I want. > Basically, I just want the bit corresponding to the sign of a-b to be > connected to c. How can I do this without the if then else statement so that > I don't get the "Illegal concurrent statement" warning. > > Thanks. > > PS : I am a beginner. c <= '1' when a < b else '0'; charles.elias@wpafb.af.mil |
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#3 |
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Posts: n/a
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<> a écrit dans le message de news: om... > > Aji wrote: >> Hi, >> >> I would like to do something like : >> >> if a < b then c <= '1'; else c <= '0'; end fi; >> >> where a and b are SIGNED vectors and c is std_logic. >> >> I get the warning "Illegal concurrent statement" because it is not >> embedded >> inside a process block. >> >> I don't really need the if then else structure to implement what I want. >> Basically, I just want the bit corresponding to the sign of a-b to be >> connected to c. How can I do this without the if then else statement so >> that >> I don't get the "Illegal concurrent statement" warning. >> >> Thanks. >> >> PS : I am a beginner. > > c <= '1' when a < b else '0'; > Thank you Charles, I'll try this. Aji Aji |
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