TCL CODE WITH VHDL

hii

i have to study TCL SCRIPTING and i have to verify the VHDL codes, i
have learnt this lannguage but have to verify the vhdl code using TCL
SCRIPT. can any one out here please tell me how to go about. Any link
or pdf doc. that explains how to do the same.
suppose i have to verify a counter. i have to force values to teh
signal, get it on the waveform. the entire process that a testbench
does, has to be performed in TCL SCRIPT...
i hope query is well explained.

thanks
HAPPY NEW YEAR TO ALL

AAA

To 'verify' VHDL code, you need a tool that can do the 'verification' that you want.
TCL is a command line interface into many tools that read VHDL.
Which tool are you using ?

Rob

"AAA" <> wrote in message news: oups.com...
> hii
>
> i have to study TCL SCRIPTING and i have to verify the VHDL codes, i
> have learnt this lannguage but have to verify the vhdl code using TCL
> SCRIPT. can any one out here please tell me how to go about. Any link
> or pdf doc. that explains how to do the same.
> suppose i have to verify a counter. i have to force values to teh
> signal, get it on the waveform. the entire process that a testbench
> does, has to be performed in TCL SCRIPT...
> i hope query is well explained.
>
> thanks
> HAPPY NEW YEAR TO ALL
>
>

Rob Dekker

hii...
i'am using modelsim PE.
you saying its a command line interface, are there any commands as such
that interfaes directly with the vhdl file, suppose the vhdl file that
has to be verified is d_ff.vhd. should i even have the testbench file
along with this or just need the d_ff.vhd file. and now to interface
the script with this ie.. with the vhdl file what should be done.
should any command be used in vsim.
how can i force values to the signals, view the wave form using the
command add wave.
can you plzz help me, as in my company i should learn this on my own,
i'am a trainee and have to get this concept clear soon. can u please
give me a example using a D Flip-Flop.

it would be great n really appreciated if you help me out..

Thanks..

thanks Rob

AAA

A Very "Happy New Year 2006" to you & your family !!!
May this year bring in Peace, Happiness, Prosperity & Good health !!!!

take care Rob...

AAA

Hi AAA,
Refer to MTI's TCL commands. Quickly:

1. One can do a "force clk 1, 10, 0, 20" (Or some thing similar) to
drive a clk.
2. Do a force/deposit to D input as required.

3. All of these commands can be put in a TCL file/do file and be given
to vsim -do ..

Good Luck
Ajeetha
www.noveldv.com

Ajeetha

thanks !!! will try doing it..
but, what is this MTI's TCL COMMAND????..

AAA

Hi,
MTI - Model Tech Inc - part of Mentor Graphics now. Essentially i wan
referring you to Modelsim's documentation, TCL command section of it.

Good Luck
Ajeetha

Ajeetha

Verifying vhdl using one tool's TCL command language is generally not a
good idea, since that script will only run on that tool. A proper
testbench, written in vhdl, will run on any vhdl simulator, and is
generally easier to write anyway, assuming you know vhdl.

Andy

Andy

yes exactly...
this is what i said.. a testbench itself will simulate and verify the
entire design.. why need a script???

set d "1"
run 200
set d "0"
run 300

this is a basic TCL script in which we carry on the stimulation. this
can be done in testbench itself. so y need script. but few other
commands like "STEP" carry on line by lione simulation that makes it
easy to verify the code. "TEST" comapres values with expected values,
and many other such commands that actually help in better verification
of the design.

so any one.. pleaseeeeeeeee help me. suppose i have a d flip-flop code
in vhd (dff.vhd). i have to verify this code using a script language.
how should i start coding in TCL. i seem to have a starting problem
here...... well.. if i get the basics right, i can proceed from here...
so please any one be helpfull and sincere tell me how to go about. what
commands are suposed to invoke the design and what actually is needed
from me being a verification engineer...

THANKS

AAA

Hi AAA,
I'm afraid you are going in the wrong direction to learn
Verification. Originally I inferred from your post that you "had to do
this in TCL" b'cos you were asked to do so (or some other reason) - but
if the objective is to learn verification, then this direction is
wrong. Learn Testbenches, they can be made self-checking too. About
"STEP" etc. - you are confusing debug with verification, when some
thing doesn't work as expected, then you go into STEP etc. (Even then
that will be last resort as it takes lot of time).

Good Luck
Ajeetha
www.noveldv.com

P.S. My consultancy company, CVC can offer an introduction to
verification course, contact me @ gmail.com <AT> ajeetha for details -
this will be a paid one though (not FREE).

Ajeetha