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TCL CODE WITH VHDL

 
 
Andy
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      01-06-2006
With vhdl, you have the ability to write a self-checking testbench that
stimulates the design, monitors the outputs, and decides if they are
correct. The best part is that if someone else runs such a testbench a
few months/years down the road, it will tell them whether the design is
correct too. So any modifications they make can still be checked to
the original specifications (plus any they want to add).

The main tool for this is vhdl's assert statement that can output
status or warnings, and even break or stop the simulation based on any
condition in the simulation. These assertions can be embedded in
particular models of the testbench, or even in the RTL code being
tested, so that they have visibility of conditions that would be very
difficult to duplicate in a script. Rather than having the limitations
of the scripting language, you have the full breadth and power of the
vhdl programming language to implement the stimulus and the
verification.

Sorry, I don't use enough commands in any simulator other than run, and
setting a few breakpoints, or selecting signals to be watched or
displayed in waveforms while I'm debugging the testbench/UUT to be able
to help you. All I'm saying is that, unless this is for an assignment
that stipulates using the simulator commands to verify the design,
you're much better off learning to do it in native vhdl. The only
reason for such an assignment is so you'll later be able to see how
much better writing self-checking testbenches is.

Try inserting some "assert false;" statements in your vhdl code (these
will always stop), then play with the condition so that it only stops
(and prints a message) if something is wrong (unexpected value, etc.).

Andy

 
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AAA
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      01-09-2006
hi ..
thanks for the reply.
well.. i just gave an example regarding STOP, STEP.
in TCL script one uses only run, run run. here the designer uses
testbesnch for self verification. stimulates the design and verifies
the output.
i should use the commands like force and run throughout my script. i
need not have a testbench. just have the script and vhdl file in the
same project and have few commands in TCL script to invoke the vhdl
file. m i right???

thanks

 
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AAA
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      01-09-2006
hii..
i have written a tsl script to verify a d flip flop. i want to use
files in tcl. any commands that take the input from a file and store in
a file plzz let me know soon...
thanks

 
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Andy
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      01-09-2006
No. Trust me (and others), your best option is learning vhdl
testbenches. For the equivalent of what you can do from a script, the
parts of vhdl you need to learn is pretty simple anyway.

Testbenches are the preferred way of verfiying a design.

With a test bench, you don't need a script. Just run the simulation,
and it tells you if you had any errors, and stops when it is done. If
you had errors, the assertions can stop the simulator then as well, so
you can investigate (step, check values, etc.)

In fact, for regression testing (testbench is already debugged, your
just trying to verify that minor design changes have not introduced
other errors), you can speed up the simulation by disabling all the
hooks for debugging, etc.

Andy

 
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AAA
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      01-10-2006
well. in my earlier verification i have used testbenches, i have used
it well to verify a design, using files, assertions, comparisons were
done using testbenches, but the comapany needs a script to be written
so i have to learn the same. using testbenches is much much simpler.
anyways. if any one has a code in tcl to use files, to use a file that
has data as inputs and to force values to it, and also to call on a
file in which expected output is stored and can i add this in a wave to
verify my result.

thanks for your post andy, its certainly appreciated.

 
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ALuPin@web.de
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      01-10-2006
Doulos offers a nice TCL course.
Have a look at their homepage.

 
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AAA
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      01-13-2006

hi.
i wana know how to capture an output and store it in text file.
say for example, i have to capture the q outfut of a D flip flop. and
storre it in a text file. how do i do this using tcl script. can any 1
here tell me. how do i capture an output signal of VJDL inot a text
file in tcl and store it.
ok
thanks
BYEE

 
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Ajeetha
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      01-13-2006
Hi,
I wonder why you won't use Google to search and find it for yourself
- it will be much faster for yourself. Anyway here is a link:

http://cslu.cse.ogi.edu/toolkit/old/...rp/node26.html

Now, with this and Modelsim's documentation you should be able to do
what you have asked.

Good Luck
Ajeetha
www.noveldv.com

 
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AAA
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      01-17-2006
well i'am a new bee in TCL scripting. well, i know how to put data in a
file, but my doubt is, how can i capture the output of a DUT using TCL
script. thats not mentioned in net..
i have to capture the output of a VHDL file and store it in a text
file.
say for example, i have to capture the output "Q" of the D FLIP-FLOP
and store this in a text file. How do i capture. i have to take the
inputs of the D F-F from a text file again which i can take it very
easily. But the output Q has to be captured, so can any one out here
help me. i'am in a fix..


i have used a F-F as an example. in general i have to capture the
output of any DUT.


thanks a lot
bye

 
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Ajeetha
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      01-17-2006
Hi AAA,
Sorry to be little harsh - why don't you read Modelsim
documentation? Look for file "se_cmds.pdf" under install dir (or PE
version if be the case). There is "examine" command to do exactly what
you need:

----
examine /top/bus1
Returns the value of /top/bus1.
---

Also see:
http://www.altera.com/support/exampl...unter_tcl.html

HTH
Ajeetha
www.noveldv.com

 
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