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Re: bidirectional bus

 
 
Arnim Laeuger
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      12-18-2005
Hi Olaf!

Guess do_wr should release the bus when the write operation has finished:

> procedure do_wr (
> constant addr : in unsigned;
> constant dat : in std_logic_vector) is
> begin
> wr <= '1';
> address <= addr;
> data <= dat;
> tic;
> wr <= '0';

data <= (others => 'Z');
> end procedure do_wr;


Also consider to initialize data to Z in the TB process. But that's a
cosmetic issue.

Cheers

Arnim
 
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Arnim Laeuger
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      12-20-2005

> thanks, I did as you mentioned, the wr proc is terminated by setting the
> data bus to HighZ. Unfortunally the 2nd read is missing in my data.


> procedure do_rd (
> constant addr : in unsigned;
> signal dat : out std_logic_vector) is
> begin
> rd <= '1';
> address <= addr;
> tic;
> dat <= data;
> rd <= '0';
> --data <= (others => 'Z'); -- same problem
> end procedure do_rd;


Procedure do_rd reads "data" on the rising clock edge when "data" still
contains the old value. The new value is scheduled by rdwr_proc during
the same delta cycle but this is not visible until simulation progresses
to the next delta cycle. That's why the expected value is visible on
"data" while "my_data" is delayed by one clock cycle.

In other words, do_rd expects that the registers can be read
asynchronously ("data" is valid during the same clock cycle) and saves
the value with the next rising clock edge. This doesn't work because the
registers are read synchronously ("data" is valid during the next clock
cycle).

For your behavioral test bench code, you could save "data" with a small
delay after the rising clock edge. Just long enough to skip all delta
cycles and the simulator increases time.

> procedure do_rd (
> constant addr : in unsigned;
> signal dat : out std_logic_vector) is
> begin
> rd <= '1';
> address <= addr;
> tic;

wait for 1 ps; -- anything > 0 fs
> dat <= data;
> rd <= '0';
> --data <= (others => 'Z'); -- same problem
> end procedure do_rd;


The synchronous way is:

> procedure do_rd (
> constant addr : in unsigned;
> signal dat : out std_logic_vector) is
> begin
> rd <= '1';
> address <= addr;
> tic;

tic;
> dat <= data;
> rd <= '0';
> --data <= (others => 'Z'); -- same problem
> end procedure do_rd;



Cheers

Arnim
 
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Olaf Petzold
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      12-20-2005
Thank you for your explanations. I will test it tomorrow.

> For your behavioral test bench code, you could save "data" with a small
> delay after the rising clock edge. Just long enough to skip all delta
> cycles and the simulator increases time.
>
> > procedure do_rd (
> > constant addr : in unsigned;
> > signal dat : out std_logic_vector) is
> > begin
> > rd <= '1';
> > address <= addr;
> > tic;

> wait for 1 ps; -- anything > 0 fs


and how can I solve it for synthesis tools, like the xilinx tools?


Thanks
Olaf
 
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