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Modelsim error: Cannot read output pain

 
 
Olaf Petzold
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Posts: n/a
 
      12-18-2005
Hi,

the code below produces the warning:

Synthesis Warning: Reset signal 'status' is not in the sensitivity
list of process 'proc'.

Well, after adding this to the sensitivity list I've got the error:
Cannot read output "status".

How stupid is Modelsim (or me)? If I change entity signal status to
inout type, it compiles but that isn't what I want. In my code the
recod is more complex. How can I fix this?

Thanks
Olaf

---8<---
library ieee;
use ieee.std_logic_1164.all;

package pkg_foo is
type status_t is record
ok : std_logic;
end record status_t;
procedure reset_status (signal status : out status_t);
end package pkg_foo;

library ieee;
use ieee.std_logic_1164.all;
use work.pkg_foo.all;

entity foo is
port (
clk : in std_logic;
reset : in std_logic;
status : out status_t);
end entity foo;

architecture behaviorial of foo is
begin
proc: process (clk, reset) is
begin
if (reset = '1') then
reset_status(status);
elsif rising_edge(clk) then
status.ok <= '1';
end if;
end process proc;
end architecture behaviorial;

package body pkg_foo is
procedure reset_status (signal status : out status_t) is
begin
status.ok <= '0';
end procedure reset_status;
end package body pkg_foo;
--->8---
 
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Balogh Viktor
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      12-18-2005
Howdy-ho,

Olaf Petzold wrote:
> Hi,
>
> the code below produces the warning:
>
> Synthesis Warning: Reset signal 'status' is not in the sensitivity list
> of process 'proc'.


Well, a warning is not an error.
If you want to do update only when clock or reset changes (I
think this is your case because there's no other possibility
-- still, who knows? ), it's ok.
It issues a warning to tell you that in a process it
*detects* that you use a value of a signal, and you may want
it to appear in the s.list. That's all. In this case, the
call of reset_status on status tells tells the syntheser
that it is an input.

>
> Well, after adding this to the sensitivity list I've got the error:
> Cannot read output "status".


Yes, it tries to read back the value, as it is in the
sensitivity list. But this is an output. So it is not readable.

>
> architecture behaviorial of foo is
> begin
> proc: process (clk, reset) is
> begin
> if (reset = '1') then
> reset_status(status);


would it be a problem to say status.ok <= 0 ?
Just to avoid confusion. Something in me is shouting that
your code is not the VHDL-way.

> elsif rising_edge(clk) then
> status.ok <= '1';
> end if;
> end process proc;
> end architecture behaviorial;
>
> package body pkg_foo is
> procedure reset_status (signal status : out status_t) is
> begin
> status.ok <= '0';
> end procedure reset_status;
> end package body pkg_foo;
> --->8---


Good luck

--
Vitya
http://www.velocityreviews.com/forums/(E-Mail Removed)
 
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Ralf Hildebrandt
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      12-18-2005
Olaf Petzold wrote:

> Synthesis Warning: Reset signal 'status' is not in the sensitivity list
> of process 'proc'.
>
> Well, after adding this to the sensitivity list I've got the error:
> Cannot read output "status".
>
> How stupid is Modelsim (or me)?


Outputs cannot be read. Modelsim should have told you this also together
with the 1st warning.

-> Make a copy from the output signal, read the copy.

Ralf
 
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Duane Clark
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Posts: n/a
 
      12-18-2005
Olaf Petzold wrote:
> Hi,
>
> the code below produces the warning:
>
> Synthesis Warning: Reset signal 'status' is not in the sensitivity
> list of process 'proc'.


Is there a reason you are putting a procedure() in the reset portion of
the process? You are confusing the synthesis tool, and it is probably
not using the builtin FPGA reset resources (assuming you are targetting
an FPGA with them).

>
> Well, after adding this to the sensitivity list I've got the error:
> Cannot read output "status".
>
> How stupid is Modelsim (or me)? If I change entity signal status to
> inout type, it compiles but that isn't what I want. In my code the
> recod is more complex. How can I fix this?


This has nothing to do with Modelsim. All simulation/synthesis tools
will do the same. VHDL is picky. Whenever you want to use an output
signal internally, you will always need to generate an internal signal,
something like:

architecture behaviorial of foo is
signal status_i : status_t;
begin
status <= status_i;
proc: process (clk, reset) is
begin
if (reset = '1') then
reset_status(status_i);
elsif rising_edge(clk) then
status_i.ok <= '1';
end if;
end process proc;
end architecture behaviorial;
 
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Duane Clark
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      12-18-2005
Duane Clark wrote:
> Olaf Petzold wrote:
>> Hi,
>>
>> the code below produces the warning:
>>
>> Synthesis Warning: Reset signal 'status' is not in the sensitivity
>> list of process 'proc'.

>
> Is there a reason you are putting a procedure() in the reset portion of
> the process? You are confusing the synthesis tool, and it is probably
> not using the builtin FPGA reset resources (assuming you are targetting
> an FPGA with them).


By the way, I guess I did not explicitly point out the reason why you
are getting the above warning. Any "source" signal in a non-clocked
portion of a process needs to be in the sensitivity list. Because you
have a procedure with status as a parameter, the synthesis tool thinks
this is a source signal, and that it should therefore be in the
sensitivity list.

In reality, your procedure merely sets the value of status, so it is not
truly a source signal. If you explicitly set the value of status within
the reset portion of the process, you will not need to put it into the
sensitivity list.

 
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Olaf Petzold
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Posts: n/a
 
      12-18-2005
first, thanks to all for the replay.

But I'm confusud. You wrote, output signals can not be read. Is this
the caller view? Until now, I've never confused on that (in and out of
entities/procedures).

The reason for using the procedure was to write clean/readable code,
since I have to reset about 20 different types of register variables
(see the problem of bidirectional bus). These reset code would be
waste a lot of the screen view. For this the procedure is inside a
package.

> Any "source" signal in a non-clocked portion of a process needs to
> be in the sensitivity list.


Well, that's important to know. I assume, the synthesis tool isn't
clever enough to find out the depency in real (maybe there are some
language specific reasons too). The use of an internal signal I will try.

Thanks and regards,
Olaf
 
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Mike Treseler
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      12-18-2005
Olaf Petzold wrote:

> But I'm confusud. You wrote, output signals can not be read. Is this the
> caller view?


"read" means putting the identifier on the right
side of the assignment. You didn't do this, so
don't worry about it. If you ever need to do it,
use a variable or signal identifier instead
of a port.

> Until now, I've never confused on that (in and out of
> entities/procedures).


I've used many synthesis tools and have
never seen one confused by a procedure.
So I wouldn't worry about that either.
Your call of:
reset_status(status);

is equivalent to the statement:
status.ok <= '0';

Either report the bogus warning to Modelsim,
or just ignore it.

-- Mike Treseler
 
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Duane Clark
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      12-18-2005
Mike Treseler wrote:
> Your call of:
> reset_status(status);
>
> is equivalent to the statement:
> status.ok <= '0';
>
> Either report the bogus warning to Modelsim,
> or just ignore it.


It is not Modelsim generating the bogus warning, it is his synthesis
tool, whatever that is.

Olaf Petzold wrote:
> Synthesis Warning: Reset signal 'status' is not in the sensitivity
> list of process 'proc'.
>


Clearly, whatever synthesis tool he is using, it is indeed confused.
 
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Olaf Petzold
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Posts: n/a
 
      12-19-2005
> architecture behaviorial of foo is
> signal status_i : status_t;
> begin
> status <= status_i;


got the same Problem here: Cannot read output. As Mike wrote, status_i
is on the right side and therefore read.

Well, I have to ignore the warning or replace the procedure with
procedure body's code.

Thanks
Olaf
 
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Mike Treseler
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      12-19-2005
Olaf Petzold wrote:

> Well, I have to ignore the warning or replace the procedure with
> procedure body's code.


check your modelsim.ini file for vhdl93:
[vcom]
; Turn on VHDL-1993 as the default. Normally is off (VHDL-1987).
VHDL93 = 1

Note that modelsim 6.1 give me
no such warning on your code:

74 steptoe Mon Dec 19 /evtfs/home/tres/vhdl/play > vcom foo.vhd
75 steptoe Mon Dec 19 /evtfs/home/tres/vhdl/play > vsim -c foo
Reading /steptoe/usr1/modeltech/tcl/vsim/pref.tcl
# 6.1b
# vsim -c foo
# // ModelSim SE 6.1b Sep 8 2005 Linux 2.6.8-24.10-default
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading work.pkg_foo(body)
# Loading work.foo(behaviorial)
VSIM 1>

Also note that quartus 5.1 gives
this rtl synth without warnings:

http://home.comcast.net/~mike_treseler/foo.pdf

-- Mike Treseler
 
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