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Coding style, wait statement, sensitivity list and synthesis.

 
 
AG
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      12-14-2005
Hi,

I am new in vhdl.

In my book, the following code is given :

entity LATCH ....
end entity;

architecture A of LATCH is
begin
process
begin
if CK='1' then
Q <= D;
QB <= not D;
end if;
wait on CK,D; -- compiler error
end process;
end A;

Compilier says during elaboration :
'Wait Statement must contain condition clause with UNTIL keyword'

If I use the sensitivity list instead, the problem disappears. (except the
fact that the behavior is not strictly equivalent).

In my book, it says that using "sensitivity list" is an old fashion way of
coding, and using the wait statement is better (more generic). Who should I
believe ?

This leads me to the following question : if not all vhdl statement are
valid, how do I write portable vhdl so that it can be compiled on several
targets ?

I use Quartus II web free edition.

Thanks.

Heydji.


 
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antonio bergnoli
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      12-14-2005
AG ha scritto:
> Hi,
>
> I am new in vhdl.
>
> In my book, the following code is given :
>
> entity LATCH ....
> end entity;
>
> architecture A of LATCH is
> begin
> process
> begin
> if CK='1' then
> Q <= D;
> QB <= not D;
> end if;
> wait on CK,D; -- compiler error

it is valid VHDL but
it is the sythesis that failed, you try to build a 2-edge triggered
clocks FF and this stuff doesnt exist in a FPGA.
> end process;
> end A;
>



> Compilier says during elaboration :
> 'Wait Statement must contain condition clause with UNTIL keyword'
>
> If I use the sensitivity list instead, the problem disappears. (except the
> fact that the behavior is not strictly equivalent).
>
> In my book, it says that using "sensitivity list" is an old fashion way of
> coding, and using the wait statement is better (more generic). Who should I
> believe ?


What's the title of this book!?

>
> This leads me to the following question : if not all vhdl statement are
> valid, how do I write portable vhdl so that it can be compiled on several
> targets ?
>
> I use Quartus II web free edition.


Important: Coding Vhdl not only mean synthesis but even simulation,
verification, autodocumentation....
>
> Thanks.
>
> Heydji.
>
>

 
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Harpreet
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      12-15-2005
Hello AG,

Even I am new to VHDL but I did a course on it as part of my undergrad
program recently.
In my opinion, your problem is quite simple. You have a statement in
your code "wait on D, CK", Now, according to this statement, the
simulation won't progress until you have events on both the signals.
However, putting them in the sensitivity list resolves your problem
because the sensitivity list checks for events on any the arguments
specified in it.

Regarding the sensitivity list being an outdated way of coding, there
might be debates on that. However, it goes without saying that wait
statements are more popular state machine coding wise.

I can't really answer your last query as I myself am novice in this
field.

Hope that helps.
-Harpreet

 
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AG
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      12-15-2005
"Harpreet" <(E-Mail Removed)> a écrit dans le message de news:
(E-Mail Removed) m...
> In my opinion, your problem is quite simple. You have a statement in
> your code "wait on D, CK", Now, according to this statement, the
> simulation won't progress until you have events on both the signals.
> However, putting them in the sensitivity list resolves your problem
> because the sensitivity list checks for events on any the arguments
> specified in it.

Sure, but why the "wait on D,CK" can't be synthesised while the same
behavior with the sensitivity list way can.

Antonio says it's because a "wait on D,CK" statement corresponds to a 2-edge
triggered clocks which doesn't exist in FPGA. But how does the synthesis do
to build the equivalent with the sensitivity list ?

Adji.


 
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Nicolas Matringe
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      12-15-2005
AG a écrit:
> Sure, but why the "wait on D,CK" can't be synthesised while the same
> behavior with the sensitivity list way can.
> Antonio says it's because a "wait on D,CK" statement corresponds to a 2-edge
> triggered clocks which doesn't exist in FPGA. But how does the synthesis do
> to build the equivalent with the sensitivity list ?


Hi
The "wait on d, ck;" statement is strictly equivalent to a sensitivity
list. It does _not_ imply a 2-edge triggered FF or anything, and it
doesn't wait for activity on both signals either.
All synthesis tools do not support 100% of the sythesizable subset of
the language. You sometimes find that what worked with some tool does
not with another.
It seems that QII does not support your wait statement, well, don't use
it and go with a sensitivity list instead.
And for your book's statement about sensitivity list, my opinion is
that it is utterly wrong.
What book is it?

Nicolas

 
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AG
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      12-15-2005

>And for your book's statement about sensitivity list, my opinion is
>that it is utterly wrong.
>What book is it?

Some french book. Probably a bad one. I have ordered a better one.

Thanks anyway.





 
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antonio bergnoli
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      12-15-2005
Nicolas Matringe ha scritto:
> AG a écrit:
>
>>Sure, but why the "wait on D,CK" can't be synthesised while the same
>>behavior with the sensitivity list way can.
>>Antonio says it's because a "wait on D,CK" statement corresponds to a 2-edge
>>triggered clocks which doesn't exist in FPGA. But how does the synthesis do
>>to build the equivalent with the sensitivity list ?

>
>
> Hi
> The "wait on d, ck;" statement is strictly equivalent to a sensitivity
> list. It does _not_ imply a 2-edge triggered FF or anything, and it
> doesn't wait for activity on both signals either.

Yes Nicolas, you're definitively right. Rereading now what i wrote
yesterday i recognize that i said a silly thing. But the statement "wait
on..." is not completely equivalent to put a sensitivity list, this is
true only if "wait on..." is the first statement after "begin" process.
Or i'm going wrong again?
> All synthesis tools do not support 100% of the sythesizable subset of
> the language. You sometimes find that what worked with some tool does
> not with another.
> It seems that QII does not support your wait statement, well, don't use
> it and go with a sensitivity list instead.
> And for your book's statement about sensitivity list, my opinion is
> that it is utterly wrong.
> What book is it?
>
> Nicolas
>

 
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Nicolas Matringe
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      12-15-2005
AG a écrit:
> Some french book. Probably a bad one.


I know a few (being french myself ), which one is it?

Nicolas

 
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Nicolas Matringe
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      12-15-2005
antonio bergnoli a écrit:
> But the statement "wait on..." is not completely equivalent to
> put a sensitivity list, this is true only if "wait on..." is the first
> statement after "begin" process. Or i'm going wrong again?


I think you're right, actually.
It doesn't make big difference except at first simulation cycle where
the process with the 'wait on' at the end is executed and the two
others are not.

Nicolas

 
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AG
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      12-15-2005
"Nicolas Matringe" <(E-Mail Removed)> a écrit dans le message de news:
> I know a few (being french myself ), which one is it?


VHDL du langage a la modélisation


 
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