Velocity Reviews > VHDL > nesting counters

# nesting counters

john
Guest
Posts: n/a

 05-08-2006
Hi,

I need some guide lines to cascade three counters. I have two 5 bit
counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
upto 32 and increment Counter B by one and when counter B will reach to
32 it will increment counter C by one. The maximum count for counter C
is 256.
Should I increment the counter B at the falling edge of the MSB of the
counter A?
Should I increment the counter C on the falling edge of the counter B?

John

Andrew FPGA
Guest
Posts: n/a

 05-08-2006
Make sure you use the same clock for all the counters. Keep it
synchronous.
e.g. increment counter B when counter A = 31.

variable countB : natural range 0 to 31;
....

--Counter B
if rising_edge(clock) then
if countA = 31 then
countB := (CountB + 1) mod 32;
end if;
end if;

john wrote:
> Hi,
>
> I need some guide lines to cascade three counters. I have two 5 bit
> counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
> upto 32 and increment Counter B by one and when counter B will reach to
> 32 it will increment counter C by one. The maximum count for counter C
> is 256.
> Should I increment the counter B at the falling edge of the MSB of the
> counter A?
> Should I increment the counter C on the falling edge of the counter B?
>
> John

john
Guest
Posts: n/a

 05-09-2006
Hi,

Thanks for the reply! I was wondering that why do we need mod 32. would
Regards
John
Andrew FPGA wrote:
> Make sure you use the same clock for all the counters. Keep it
> synchronous.
> e.g. increment counter B when counter A = 31.
>
> variable countB : natural range 0 to 31;
> ...
>
> --Counter B
> if rising_edge(clock) then
> if countA = 31 then
> countB := (CountB + 1) mod 32;
> end if;
> end if;
>
>
>
>
> john wrote:
> > Hi,
> >
> > I need some guide lines to cascade three counters. I have two 5 bit
> > counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
> > upto 32 and increment Counter B by one and when counter B will reach to
> > 32 it will increment counter C by one. The maximum count for counter C
> > is 256.
> > Should I increment the counter B at the falling edge of the MSB of the
> > counter A?
> > Should I increment the counter C on the falling edge of the counter B?
> >
> > John

Andrew FPGA
Guest
Posts: n/a

 05-09-2006
Hi John,
Mod forces the rollover from 31 to 0. Actually XST(xilinx) won't
synthesise the mod operator if your count variable is not a power of 2
range. Instead you could test for the count = 31 and then assign 0 to
the count to achieve rollover.
Regards
Andrew

john wrote:
> Hi,
>
> Thanks for the reply! I was wondering that why do we need mod 32. would
> Regards
> John
> Andrew FPGA wrote:
> > Make sure you use the same clock for all the counters. Keep it
> > synchronous.
> > e.g. increment counter B when counter A = 31.
> >
> > variable countB : natural range 0 to 31;
> > ...
> >
> > --Counter B
> > if rising_edge(clock) then
> > if countA = 31 then
> > countB := (CountB + 1) mod 32;
> > end if;
> > end if;
> >
> >
> >
> >
> > john wrote:
> > > Hi,
> > >
> > > I need some guide lines to cascade three counters. I have two 5 bit
> > > counters ( A and B) and one 14 bit counter ( C). Counter 'A' counts
> > > upto 32 and increment Counter B by one and when counter B will reach to
> > > 32 it will increment counter C by one. The maximum count for counter C
> > > is 256.
> > > Should I increment the counter B at the falling edge of the MSB of the
> > > counter A?
> > > Should I increment the counter C on the falling edge of the counter B?
> > >
> > > John

john
Guest
Posts: n/a

 05-11-2006
Hi,

I nee CountB, Count C and CountA are in different processes. How can I
make them shared in different processes. first I do not know how to
make them global. Advice needed! and then will it create any problems
later.

Thanks
John

Mike Treseler
Guest
Posts: n/a

 05-11-2006
john wrote:

> I nee CountB, Count C and CountA are in different processes.

Why? Simpler is better.

> How can I
> make them shared in different processes.

Processes communicate using signals.
Look it up.

-- Mike Treseler

john
Guest
Posts: n/a

 05-18-2006
Hi,

But the problem is that my design needs to increment the counters on
the falling edge of the MSB bit. That will take the main clock away
from the counters and they will not be synchronous anymore. how can I
do it without removing the clock and on the falling edge of the MSB
bit.

John

Mike Treseler
Guest
Posts: n/a

 05-18-2006
john wrote:

> But the problem is that my design needs to increment the counters on
> the falling edge of the MSB bit. That will take the main clock away
> from the counters and they will not be synchronous anymore. how can I
> do it without removing the clock and on the falling edge of the MSB
> bit.

Generate a synchronous strobe
and use that as an enable.

-- Mike Treseler

john
Guest
Posts: n/a

 05-18-2006

Can u advice me example code?

John

Mike Treseler
Guest
Posts: n/a

 05-18-2006
john wrote:
> Can u advice me example code?

search for "strobe" here:
http://home.comcast.net/~mike_treseler/rise_count.pdf
http://home.comcast.net/~mike_treseler/rise_count.vhd

-- Mike Treseler