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Hi,

Does anyone know of a tool which will import a set of VHDL design files
and produce a block diagram showing the component interconnections
(without any RTL
translation unlike Xilinx ISE schematic viewer) ?

Thanks

http://groups.google.com/group/comp....cda5c163da6d03

hi,
Every simulation window has an option to see the schematic of the
design like
ncsim of cadence has simvision
debussy of novas shows schematic with good clarity ....

regards,
Anupam Jain

schrieb:
> Hi,
>
> Does anyone know of a tool which will import a set of VHDL design files
> and produce a block diagram showing the component interconnections
> (without any RTL
> translation unlike Xilinx ISE schematic viewer) ?

I belive HDL Designer by Mentor has a HDL2Graphics feature. I never
tried it.

Bye Tom

indeed, ncsim has simvision to draw blockdiagrams and it works very nice!
You can use simvision for debugging your (top level) code as well.

--
----------------------------------------------
<> wrote in message
news: ups.com...
> Hi,
>
> Does anyone know of a tool which will import a set of VHDL design files
> and produce a block diagram showing the component interconnections
> (without any RTL
> translation unlike Xilinx ISE schematic viewer) ?
>
> Thanks
>

Marc Horemans wrote:
> indeed, ncsim has simvision to draw blockdiagrams and it works very nice!
> You can use simvision for debugging your (top level) code as well.
>
> --
> ----------------------------------------------
> <> wrote in message
> news: ups.com...
>> Hi,
>>
>> Does anyone know of a tool which will import a set of VHDL design files
>> and produce a block diagram showing the component interconnections
>> (without any RTL
>> translation unlike Xilinx ISE schematic viewer) ?
>>
>> Thanks
>>
>
>
Aldec's Active-HDL hac Code2Graphics that converts Verilog or VHDL to
Diagrams without simulation:

http://www.aldec.com/products/active...code2graphics/
http://www.aldec.com/products/active...vies/code2fsm/


Also it has so called Advanced Dataflow that shows the interconnects and
interactions between processes and signals in the design when simulation
is initialized:

http://www.aldec.com/products/active...nced_dataflow/

Mariusz

Mariusz & all who replied,

Thanks for the suggestions for s/w to show interconnection between
instantiated components in a VHDL design. I was looking for a low cost
solution to automate documentation of designs but it seems that I'd
have to outlay quite a bit of cash to get this feature (I'd get many
others with it though). I think I'll stick with the manual approach for
now!

Thanks
Dave

wrote:


> I was looking for a low cost
> solution to automate documentation of designs but it seems that I'd
> have to outlay quite a bit of cash to get this feature

emacs vhdl-mode speedbar will give you most of
what you want for zero cash:
http://opensource.ethz.ch/emacs/vhdl-mode.gif

-- Mike Treseler

Mike,
Thanks for the suggestion but I'm looking for something that can
document a design that a non-HDL engineer can easily follow i.e. block
diagram.
Thanks
Dave

wrote:
> Mike,
> Thanks for the suggestion but I'm looking for something that can
> document a design that a non-HDL engineer can easily follow i.e. block
> diagram.
> Thanks
> Dave

Hi Dave, try www.expressivesystems.com where there is a fully
functional demo download of Expressive-IV

Brian