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Test bench

 
 
Vitaliy
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      11-21-2005
Hi,
I'm trying to simulate this in Cadence:
http://www.csee.umbc.edu/help/VHDL/samples/bmul32.vhdl

I don't have any problems with that,I can compile the files using
"ncvhdl -v93". I can also import the files in Synopsis and get gate
level as expected.

However, when I try to compile
http://www.csee.umbc.edu/help/VHDL/s...ul32_test.vhdl
I get this error.
ncvhdl: 05.10-p004: (c) 1995-2003 Cadence Design Systems, Inc.
ncvhdl_p: *internal* (expecting FUNCTION of PROCEDURE).
Please contact Cadence Design Systems about this problem and provide
enough information to help us reproduce is it.

I'm really stuck on this. Any help would be much appreciated.

 
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wpiman@aol.com
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      11-21-2005
For one thing....

procedure my_printout(a : std_logic_vector(31 downto 0);
b : std_logic_vector(31 downto 0);
prod: std_logic_vector(63 downto 0)) is

You need to declare the direction of these signals in a procedure. ie.

procedure my_printout(a : IN std_logic_vector(31 downto 0);

I am not sure if that is the whole issue or not- but that is what jumps
out.

 
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Vitaliy
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      11-22-2005
Thanks. I'll try that tomorrow and post the result if that was enough
to solve the problem.


http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> For one thing....
>
> procedure my_printout(a : std_logic_vector(31 downto 0);
> b : std_logic_vector(31 downto 0);
> prod: std_logic_vector(63 downto 0)) is
>
> You need to declare the direction of these signals in a procedure. ie.
>
> procedure my_printout(a : IN std_logic_vector(31 downto 0);
>
> I am not sure if that is the whole issue or not- but that is what jumps
> out.


 
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Vitaliy
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      11-23-2005
Unfortunately, that did not help.

 
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Mike Treseler
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      11-23-2005
Vitaliy wrote:

> I'm really stuck on this. Any help would be much appreciated.



Both compile fine when I do this.

-- a1: entity WORK.add32 port map(sum_in, bb, cin, psum, cout);
-- a2: entity WORK.fadd port map(sum_in(31), topbit, cout,topout,nc1);

-- Mike Treseler
 
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Vitaliy
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      11-23-2005
Mike,
But would it make sense to modify source file to get the test bench to
work? Because source file seems to be fine, at least based on what I
see in Synopsis, and if those two lines are commented out, wouldn't
that change the functionality (btw, did you create WORK subdirectory?
depending on whether you use Linux or Windows(does Cadence even run on
Windows? not sure), you might need it). And did you have those two
files (fadd.vhdl and add32.vhdl) in the same directory as bmul32.vhdl?
Because that could be a reason bmul32.vhdl did not compile.
Thanks for the help, I will try that tomorrow,


Mike Treseler wrote:
> Vitaliy wrote:
>
> > I'm really stuck on this. Any help would be much appreciated.

>
>
> Both compile fine when I do this.
>
> -- a1: entity WORK.add32 port map(sum_in, bb, cin, psum, cout);
> -- a2: entity WORK.fadd port map(sum_in(31), topbit, cout,topout,nc1);
>
> -- Mike Treseler


 
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Mike Treseler
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      11-23-2005
Vitaliy wrote:

> But would it make sense to modify source file to get the test bench to
> work?


Step one is to find the error.

> And did you have those two
> files (fadd.vhdl and add32.vhdl) in the same directory as bmul32.vhdl?


Did you?
Those were not mentioned in your posting.

-- Mike Treseler
 
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Vitaliy
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      11-23-2005
Yes, I did.

Sorry, missed it in the first post.

Here is the code for fadd.vhdl
library IEEE;
use IEEE.std_logic_1164.all;

entity fadd is -- full adder stage, interface
port(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end entity fadd;

architecture circuits of fadd is -- full adder stage, body
begin -- circuits of fadd
s <= a xor b xor cin after 1 ns;
cout <= (a and b) or (a and cin) or (b and cin) after 1 ns;
end architecture circuits; -- of fadd

here is the code for add32.vhdl

library IEEE;
use IEEE.std_logic_1164.all;
entity add32 is -- simple 32 bit ripple carry adder
port(a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end entity add32;

architecture circuits of add32 is
signal c : std_logic_vector(0 to 30); -- internal carry signals
begin -- circuits of add32
a0: entity WORK.fadd port map(a(0), b(0), cin, sum(0), c(0));
stage: for I in 1 to 30 generate
as: entity WORK.fadd port map(a(I), b(I), c(I-1) , sum(I),
c(I));
end generate stage;
a31: entity WORK.fadd port map(a(31), b(31), c(30) , sum(31), cout);
end architecture circuits; -- of add32

 
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Mike Treseler
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      11-23-2005
Vitaliy wrote:
> Yes, I did.
>
> Sorry, missed it in the first post.
> Here is the code for fadd.vhdl
> here is the code for add32.vhdl


That significantly improves the performance.

-- Mike Treseler
__________________________
69 steptoe Wed Nov 23 /evtfs/home/tres/vhdl/play > vsim -c bmul32_test
Reading /steptoe/usr1/modeltech/tcl/vsim/pref.tcl
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading /steptoe/usr1/modeltech/linux/../std.textio(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_textio(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_arith(body)
# Loading work.bmul32_test(circuits)
# Loading work.bmul32(circuits)
# Loading work.badd32(circuits)
# Loading work.add32(circuits)
# Loading work.fadd(circuits)
VSIM 1> run 1 us
# Driver starting.
# a=11111111, b=11111111, prod=0123456787654321, cntr=0001, at=319 ns
#
# a=22222222, b=22222222, prod=048D159E0C83FB73, cntr=0010, at=639 ns
#
# a=44444444, b=44444444, prod=1234567876543210, cntr=0100, at=959 ns
#
VSIM 2>
 
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Vitaliy
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      11-29-2005
I have a feeling that my school doesn't have all the proper
libraries/licenses then.
Thank You, Mike.

 
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