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library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity rec_and_r is generic(and_width : integer); port( and_In : in slv(and_width-1 downto 0); clkIn : in sl; sysResetIn : in sl; and_Out : out sl); end rec_and_r; architecture rtl of rec_and_r is constant MAXANDWIDTH : integer := 4; component and_r generic(and_width : integer); port( and_In : in slv(and_width-1 downto 0); clkIn : in sl; sysResetIn : in sl; and_Out : out sl); end component; begin single_and_structure : if (and_width <= MAXANDWIDTH) generate begin U1 : and_r generic map(and_width => and_width) port map( and_In => and_In, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Out); end generate single_and_structure; multiple_and_structure : if (and_width > MAXANDWIDTH) generate signal and_Sig : slv(integer(ceil(real(and_width)/real(MAXANDWIDTH)))-1 downto 0); -- bus for all the registered and gate outputs begin full_width_and_structure : for genLoopVar in 0 to integer(floor(real(and_width)/real(MAXANDWIDTH)))-1 generate begin U1 : and_r generic map(and_width => MAXANDWIDTH) port map( and_In => and_In(MAXANDWIDTH*genLoopVar+MAXANDWIDTH-1 downto MAXANDWIDTH*genLoopVar), clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Sig(genLoopVar)); end generate full_width_and_structure; partial_width_and_structure : if ((and_width mod MAXANDWIDTH) /= 0) and (and_width /= 0) generate begin U2 : and_r generic map(and_width => and_width mod MAXANDWIDTH) port map( and_In => and_In(and_In'high downto and_In'high - and_width mod MAXANDWIDTH), clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Sig(and_Sig'high)); end generate partial_width_and_structure; recursive_and_structure : if and_Sig'length /= 1 generate begin U3 : and_r generic map(and_width => and_Sig'length) port map( and_In => and_Sig, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Out); end generate recursive_and_structure; end generate multiple_and_structure; end rtl; library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity and_r is generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_Out : out std_logic); end and_r; architecture rtl of and_r is begin compProc : process(ClkIn, SysResetIn) constant ones : std_logic_vector(and_In'range) := (others => '1'); begin if (SysResetIn = '1') then and_Out <= '0'; elsif rising_edge(clkIn) then if (and_In = ones) then and_Out <= '1'; else and_Out <= '0'; end if; end if; end process; end rtl; library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity comparator_r is generic(bus_width : integer); port( aIn : in std_logic_vector(bus_width-1 downto 0); bIn : in std_logic_vector(bus_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; eqOut : out std_logic ); end comparator_r; architecture rtl of comparator_r is begin compProc : process(ClkIn, SysResetIn) begin if (SysResetIn = '1') then eqOut <= '0'; elsif rising_edge(clkIn) then if (aIn = bIn) then eqOut <= '1'; else eqOut <= '0'; end if; end if; end process; end rtl; ------------------------------------------------------------------------------ -- -- author : Michael Bills () -- -- description : This package has functions and procedures -- for testbenching and assisting in RTL design -- creation. It consists mostly of conversion functions. -- This is a two-part package. The package testbench is -- included at the bottom begining around line 4560. -- -- -- -- -- Copyright (c) 2005 by Michael Bills -- -- Permission to use, copy, modify, distribute, and sell this source code -- for any purpose is hereby granted without fee, provided that -- the above copyright notices and this permission notice appear -- in all copies of this source code. -- -- THIS SOURCE CODE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, -- EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, -- ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. -- -- THE USER OF THIS SOURCE CODE ASSUMES ALL LIABILITY FOR THEIR USE -- OF THIS SOURCE CODE. -- -- IN NO EVENT SHALL MICHAEL BILLS BE LIABLE FOR ANY SPECIAL, INCIDENTAL, -- INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER -- RESULTING FROM LOSS OF USE, DATA, OR PROFITS, WHETHER OR NOT ADVISED OF -- THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING -- OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. -- ------------------------------------------------------------------------------ -- LIBRARY STATEMENT library extension_lib, ieee; -- PACKAGE STATEMENT --use extension_lib.extension_pack_constants.all; --use extension_lib.extension_pack_lfsr_str_constants.al l; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed."abs"; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------ package extension_pack is ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- Type Declarations ------------------------------------------------------------------------------ type hexchar is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'); type hex is array (positive range <>) of hexchar; type LED_Char is (' ', '"', ''', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '=', '?', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'O', 'P', 'S', 'T', 'U', 'Y', 'Z', '\', ']', '^', '_', 'b', 'c', 'd', 'h', 'g', 'j', 'l', 'n', 'o', 'r', 'u', '¬', '*', '¯', '°', '·'); type SevenSegLED is array (positive range <>) of LED_Char; -- synopsys translate_off type frequency is range 1 to 2_147_483_647 units Hz; daHz = 10 Hz; -- dekahertz 10E+1 hHz = 10 daHz; -- hectohertz 10E+2 kHz = 10 hHz; -- kilohertz 10E+3 MHz = 1000 kHz; -- megahertz 10E+6 GHz = 1000 MHz; -- gigahertz 10E+9 end units; -- synopsys translate_on ------------------------------------------------------------------------------ -- Subtype Declarations ------------------------------------------------------------------------------ --subtype bv is bit_vector; --subtype char is character; ---- synopsys translate_off --subtype fok is file_open_kind; --subtype fos is file_open_status; --subtype freq is frequency; ---- synopsys translate_on --subtype int is integer; --subtype nat is natural; --subtype pos is positive; --subtype sl is std_logic; --subtype slv is std_logic_vector; --subtype str is string; --subtype sul is std_ulogic; --subtype sulv is std_ulogic_vector; --subtype uns is unsigned; ------------------------------------------------------------------------------ -- Constant Declarations ------------------------------------------------------------------------------ -- count_for_time base size, that is to say, the smallest time value -- that is used for this function. (-60 means the timebase = 10E-60 seconds). -- VHDL uses a "timebase" or base unit of 1 fs (time'pos(1 fs) = 1) -- this value should be increased if round off error occurs -- in a value computed by the function "count_for_time" or if -- array length errors similar to this occur: -- # ** Fatal: (vsim-3420) Array lengths do not match. Left is (96 downto 0). Right is (97 downto 0). -- -- This value must be smaller than MAX_VECT_SIZE by a factor of 4 for -- logic vectors 2 bits long and it must be smaller by a factor of 3.5 for -- logic vectors longer than 2 bits constant CFT_BASE_SIZE : integer := -27; -- this value represents the largest size a logic vector may be for certain -- functions and procedures in this package. It is used to set upper loop -- limits for non-deterministic values thus avoiding the use of access -- types and enabling the functions to be used for synthesizeable code. -- -- This value may be increased (as high as natural'high will allow) -- if a larger value needs to be represented, or it may be decreased -- if compile time is excessive by modifying the CFT_BASE_SIZE constant constant MAX_VECT_SIZE : natural := (-CFT_BASE_SIZE)*4; constant LOG_PATH : string := "../../logs/"; -- location to place log files constant LOG_EXT : string := ".txt"; -- log file extention constant SRC_PATH : string := "../../src/"; -- location to access/place VHDL source files constant SRC_EXT : string := ".vhd"; -- VHDL source file extension -- LFSR pre-computed constant package width bounds constant LFSRLowerBound : integer := 2; constant LFSRUpperBound : integer := 12; type LFSR_Polynomial_Exponents_type is array(2 to 16  of string(1 to 20);-- http://direct.xilinx.com/bvdocs/appnotes/xapp052.pdf -- must be both primitive and prime to give a sequence of lenth 2**N-1 constant LFSR_Polynomial_Exponents : LFSR_Polynomial_Exponents_type :=( "2,1 ","3,2 ","4,3 ","5,3 ","6,5 ","7,6 ","8,6,5,4 ","9,5 ","10,7 ", "11,9 ","12,6,4,1 ","13,4,3,1 ","14,5,3,1 ","15,14 ","16,15,13,4 ","17,14 ","18,11 ","19,6,2,1 ","20,17 ", "21,19 ","22,21 ","23,18 ","24,23,22,17 ","25,22 ","26,6,2,1 ","27,5,2,1 ","28,25 ","29,27 ","30,6,4,1 ", "31,28 ","32,22,2,1 ","33,20 ","34,27,2,1 ","35,33 ","36,25 ","37,5,4,3,2,1 ","38,6,5,1 ","39,35 ","40,38,21,19 ", "41,38 ","42,41,20,19 ","43,42,38,37 ","44,43,18,17 ","45,44,42,41 ","46,45,26,25 ","47,42 ","48,47,21,20 ","49,40 ","50,49,24,23 ", "51,50,36,35 ","52,49 ","53,52,38,37 ","54,53,18,17 ","55,31 ","56,55,35,34 ","57,50 ","58,39 ","59,58,38,37 ","60,59 ", "61,60,46,45 ","62,61,6,5 ","63,62 ","64,63,61,60 ","65,47 ","66,65,57,56 ","67,66,58,57 ","68,59 ","69,67,42,40 ","70,69,55,54 ", "71,65 ","72,66,25,19 ","73,48 ","74,73,59,58 ","75,74,65,64 ","76,75,41,40 ","77,76,47,46 ","78,77,59,58 ","79,70 ","80,79,43,42 ", "81,77 ","82,79,47,44 ","83,82,38,37 ","84,71 ","85,84,58,57 ","86,85,74,73 ","87,74 ","88,87,17,16 ","89,51 ","90,89,72,71 ", "91,90,8,7 ","92,91,80,79 ","93,91 ","94,73 ","95,84 ","96,94,49,47 ","97,91 ","98,87 ","99,97,54,52 ","100,63 ", "101,100,95,94 ","102,101,36,35 ","103,94 ","104,103,94,93 ","105,89 ","106,91 ","107,105,44,42 ","108,77 ","109,108,103,102 ","110,109,98,97 ", "111,101 ","112,110,69,67 ","113,104 ","114,113,33,32 ","115,114,101,100 ","116,115,46,45 ","117,115,99,97 ","118,85 ","119,111 ","120,113,9,2 ", "121,103 ","122,121,63,62 ","123,121 ","124,87 ","125,124,18,17 ","126,125,90,89 ","127,126 ","128,126,101,99 ","129,124 ","130,127 ", "131,130,84,83 ","132,103 ","133,132,82,81 ","134,77 ","135,124 ","136,135,11,10 ","137,116 ","138,137,131,130 ","139,136,134,131 ","140,111 ", "141,140,110,109 ","142,121 ","143,142,123,122 ","144,143,75,74 ","145,93 ","146,145,87,86 ","147,146,110,109 ","148,121 ","149,148,40,39 ","150,97 ", "151,148 ","152,151,87,86 ","153,152 ","154,152,27,25 ","155,154,124,123 ","156,155,41,40 ","157,156,131,130 ","158,157,132,131 ","159,128 ","160,159,142,141 ", "161,143 ","162,161,75,74 ","163,162,104,103 ","164,163,151,150 ","165,164,135,134 ","166,165,128,127 ","167,161 ","168,166,153,151 " ); ------------------------------------------------------------------------------ -- Function Declarations ------------------------------------------------------------------------------ function "*"(MultiplicandVal : integer; MultiplierVal : std_logic_vector) return std_logic_vector; function "*"(MultiplicandVal : std_logic_vector; MultiplierVal : integer) return std_logic_vector; function "/"(DividendVal : std_logic_vector; DivisorVal : std_logic_vector) return std_logic_vector; function "/"(DividendVal : std_logic_vector; DivisorVal : integer) return std_logic_vector; function "/"(DividendVal : string; DivisorVal : integer) return std_logic_vector; function bcd_to_led(slvVal : std_logic_vector ; CAVal : boolean) return std_logic_vector; -- binary coded decimal to seven segment LED conversion function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed function bcd_to_slv_pipe(BCD_RVal : std_logic_vector; BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector; -- repackaging of "To_StdLogicVector" function function cdft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified (minus a count of 2 for latency) using the frequency (or period) value passed as a reference function cdft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector; -- count for the time specified (minus a count of 2 for latency) using the frequency (or period) value passed as a reference and the natural value passed as a length for the vector (if it will fit in a vector that size) function cdfth(timeStrVal : string; freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified (minus a count of 2) using the frequency (or period) value passed as a reference function ceil(RealVal : in real) return real; -- rounds a real value up the the next highest real integer function cfi(intVal : integer) return natural; -- This function returns a natural representing the number of characters required to reprsent an integer value. It is essentially an integer'length function for the characters. function cft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference function cft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference and the integer value passed as a length for the vector (if it will fit in a vector that size) function cfth(timeStrVal : string; freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference function cftu(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference, return an unsigned std_logic_vector function cftu(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector; -- count for the time specified, plus (or minus) the fudge factor, using the frequency (or period) value passed as a reference, return an unsigned std_logic_vector function clkcnt(freq1StrVal : string; freq2StrVal : string) return std_logic_vector; -- create a 50% duty cycle count time using the frequency (or period) value passed as a reference function conv_to_hex(vectorVal : bit_vector) return string; -- bit_vector to hexadecimal conversion function conv_to_hex(vectorVal : std_logic_vector) return string; -- std_logic_vector to hexadecimal conversion function conv_to_hex(vectorVal : std_ulogic_vector) return string; -- std_ulogic_vector to hexadecimal conversion function crc16(serialInVal : std_logic; vectorVal : std_logic_vector) return std_logic_vector; -- returns the input to a Cyclic Redundancy Check (CRC) using the polynomial x^16 + x^15 + x^2 + 1. function cslv(int1Val : integer; int2Val : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" function cslv(sigVal : signed; intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" function cslv(usgVal : unsigned; intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" function cuft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified (minus a count of 1 for latency) using the frequency (or period) value passed as a reference function cuft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector; -- count for the time specified (minus a count of 1 for latency) using the frequency (or period) value passed as a reference and the integer value passed as a length for the vector (if it will fit in a vector that size) function cufth(timeStrVal : string; freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference function dpfi(intVal : integer) return natural; -- returns the number of decimal places for an integer value function dpfi_syn(intVal : integer) return natural; -- returns the number of decimal places for an integer value function dpfr(realVal : real) return natural; -- returns the number of decimal places to the left of the decimal point for a real value function dpfslvr(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the full range of the std_logic_vector passed function dpfslvv(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the value of the std_logic_vector passed function eq(vector1Val : std_logic_vector; vector2Val : std_logic_vector) return boolean; -- equality check function that is sensitive to vector length function ext(strVal : string; natVal : natural) return string; -- returns a string, padded with spaces, to the length specified by intVal unless the string is already longer than that function ext2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector; -- returns a standard logic vector, padded with zeros, to the length specified by intVal unless the vector is already longer than that function flip(vectorVal : bit_vector) return bit_vector; -- returns a bit_vector with all the bits in the reverse order function flip(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector with all the bits in the reverse order function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector; -- returns a std_ulogic_vector with all the bits in the reverse order function floor(RealVal : in real) return real; -- rounds a real value down the the next loweest real integer function hex_to_slv(stringVal : string) return std_logic_vector; -- converts a Hexadeximal string to a standard logic vector function int_to_slv(intVal : integer) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the integer value passed function itoa(intVal : integer) return string; -- common integer to string conversion function function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string; polynomialStrVal : string) return std_logic_vector; -- returns the input to a Linear Feedback Shift Register (LFSR) using the polynomial function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string) return std_logic_vector; -- returns the input to a Linear Feedback Shift Register (LFSR) using a primitive polynomial function lfsr(vectorVal : std_logic_vector) return std_logic_vector; -- returns the input to a Linear Feedback Shift Register (LFSR) using a primitive polynomial. This function defaults to Type 2 XOR feedback. function lfsr_cft(timeStrVal : string; freqStrVal : string; seedVal : std_logic_vector; lfsrTypeVal : string; fudgeStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified, plus (or minus) the fudge factor, using the frequency (or period) value passed as a reference and the seed value passed as a starting point function lfsr_cft(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified, plus (or minus) the fudge factor, using the frequency (or period) value passed as a reference function lfsr_cft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference function lfsr_cft_piped(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference (for use in creating counters that have pipelined comparator stop value detection) function lfsr_cft_piped_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference (for use in creating counters that have pipelined comparator stop value detection), better suited for synthesis, (other function works also) function lfsr_cft_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference (for use in creating counters that have pipelined comparator stop value detection), better suited for synthesis, (other function works also) function lfsr_cfth(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return integer; -- repackaging of cfth for ease of lfsr use, plus (or minus) the fudge factor function lfsr_cfth(timeStrVal : string; freqStrVal : string) return integer; -- repackaging of cfth for ease of lfsr use function max(int1Val : integer; int2Val : integer) return integer; -- returns the maximum of the two values passed function mult_s(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector; -- signed multiply function mult_us(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector; -- unsigned multiply function nat_to_slv(natVal : natural) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the natural value passed function neg(VectorVal : std_logic_vector) return std_logic_vector; -- returns the negated value -- synopsys translate_off impure function now return string; -- returns a string representation of the current simulation time -- synopsys translate_on function pipelined_comparator_latency(busWidthVal : integer) return string; -- returns the latency value function pipelined_comparator_latency(timeStrVal : string; freqStrVal : string) return string; -- returns the latency value function reduce(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed (including a sign bit) function reduce_high(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'high value of a vector just large enough to represent the standard logic vector value passed (including a sign bit) function reduce_high_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'high value of a vector just large enough to represent the standard logic vector value passed function reduce_length(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed (including a sign bit) function reduce_length_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed function reduce_unsigned(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed function roundup(int1Val : integer; int2Val : integer) return integer; -- rounds an integer value up the the next higher multiple of the integer passed function rounddown(int1Val : integer; int2Val : integer) return integer; -- This function rounds the first integer value down to the next lower multiple of the second integer passed function seq(str1Val : string; str2Val : string) return boolean; function shl(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector; function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed function slv_to_bcd(vectorVal : std_logic_vector; BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified function slv_to_bcd_pipe(BCD_RVal : std_logic_vector; MSB_Val : std_logic; BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value function str_to_int(stringVal : string) return integer; -- converts an Integer string to an integer -- synopsys translate_off function str_to_line(strVal : string) return line; -- synopsys translate_on function str_to_led(stringVal : string; CAVal : boolean) return std_logic_vector; -- converts a Hexadecimal string of any length to a std_logic_vector for seven segment LEDs function str_to_slv(stringVal : string) return std_logic_vector; -- converts a string, of any length to a std_logic_vector function strh(stringVal : string) return integer; function strval_to_slv(stringVal : string) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector function strval_to_slv(stringVal : string; intVal : integer) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector using the time base passed function strval_to_slv_high(stringVal : string) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed function strval_to_slv_var_base_high(stringVal : string; intVal : integer) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed using the timebase value function sxt2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector; -- returns a standard logic vector, padded with sign bits, to the length specified by intVal unless the vector is already longer than that function to_int(vectorVal : std_logic_vector) return integer; -- repackaging of "conv_integer" function -- synopsys translate_off function to_period(freqVal : frequency) return time; -- returns a one cycle period value for a given frequency --function to_period(freqVal : string) return time; -- returns a one cycle period value for a given frequency -- synopsys translate_on function to_string(boolVal : boolean) return string; -- returns the string representation of a boolean value passed function to_string(intVal : integer) return string; -- returns the string representation of an integer value passed function to_string(realVal : real) return string; -- returns the string representation of a real value passed function to_string(timeVal : time) return string; -- returns the string representation of a time value passed function to_string(vectorVal : std_logic_vector) return string; -- returns the string representation of a std_logic_vector value passed function vhfi(intVal : integer) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the integer value passed. This assumes the rest of the range declaration of the vector will be "downto 0" function vhfn(natVal : natural) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the natural value passed. This assumes the rest of the range declaration of the vector will be "downto 0" function vlfi(intVal : integer) return natural; -- returns an integer representing the length of a vector needed to represent the integer value passed function vlfn(natVal : natural) return natural; -- returns an integer representing the length of a vector needed to represent the natural value passed function vrfi(intVal : integer) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the integer value passed function vrfn(natVal : natural) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the natural value passed function xnor_reduce(vectorVal : std_logic_vector) return std_logic; -- multiple input xnor gate function xor_reduce(vectorVal : std_logic_vector) return std_logic; -- multiple input xor gate ------------------------------------------------------------------------------ -- Procedure Declarations ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( constant clkFreqSig : in frequency; signal clkSig : out std_logic); procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; signal clkSig : out std_logic); procedure clkgen( signal clkEnSig : in boolean; signal clkPeriodSig : in time; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic); procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic); -- synopsys translate_on procedure FF( signal Clk : in std_logic; signal Rst : in std_logic; signal D : in std_logic_vector; signal Q : out std_logic_vector); procedure slv_to_bcd( signal BCD_RIn : in std_logic_vector; signal BinIn : in std_logic_vector; signal BinFBIn : in std_logic_vector; signal ClkIn : in std_logic; constant BCD_DigitsVal : in integer; signal EnIn : in std_logic; signal RstLowIn : in std_logic; signal BCD_ROut : out std_logic_vector; signal Bin_ROut : out std_logic_vector; signal DoneOut : out std_logic); ------------------------------------------------------------------------------ -- Aliases ------------------------------------------------------------------------------ -- synopsys translate_off alias bool is boolean; alias bv is bit_vector; alias char is character; alias fok is file_open_kind; alias fos is file_open_status; alias freq is frequency; alias int is integer; alias nat is natural; alias pos is positive; alias sl is std_logic; alias slv is std_logic_vector; alias str is string; alias sul is std_ulogic; alias sulv is std_ulogic_vector; alias uns is unsigned; -- synopsys translate_on ------------------------------------------------------------------------------ end extension_pack; ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ package body extension_pack is ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- Functions -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "*" -- -- DESCRIPTION : This function multiplies an integer by a -- std_logic_vector and returns a std_logic_vector -- -- NOTES : -- ------------------------------------------------------------------------------ function "*"(MultiplicandVal : integer; MultiplierVal : std_logic_vector) return std_logic_vector is begin return int_to_slv(MultiplicandVal)*MultiplierVal; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "*" -- -- DESCRIPTION : This function multiplies a std_logic_vector by an integer -- and returns a std_logic_vector -- -- NOTES : -- ------------------------------------------------------------------------------ function "*"(MultiplicandVal : std_logic_vector; MultiplierVal : integer) return std_logic_vector is begin return MultiplicandVal*int_to_slv(MultiplierVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "/" -- -- DESCRIPTION : This function divides an unsigned std_logic vector value -- by another unsigned std_logic_vector value and returns -- a std_logic_vector that is the same length -- as the dividend -- -- NOTES : the algorithm used in this function -- is the standard long division algorithm. -- it rounds to the nearest value -- ------------------------------------------------------------------------------ function "/"(DividendVal : std_logic_vector; DivisorVal : std_logic_vector) return std_logic_vector is variable DividendVar : std_logic_vector(DividendVal'length+DivisorVal'len gth downto 0); variable DivisorVar : std_logic_vector(DivisorVal'length downto 0); variable InterimVar : std_logic_vector(DivisorVal'length downto 0); variable ResultVar : std_logic_vector(DividendVal'length downto 0); begin DividendVar := ext(DividendVal & '0',DividendVar'length); DivisorVar := '0' & DivisorVal; InterimVar := '0' & DividendVar(DividendVar'high downto DividendVar'high-(DivisorVar'length-2)); ResultVar := (others => '0'); for loopVar in ResultVar'range loop if (InterimVar >= DivisorVar) then InterimVar := InterimVar - DivisorVar; InterimVar := InterimVar(InterimVar'high-1 downto 0) & DividendVar(loopVar); ResultVar(loopVar) := '1'; else InterimVar := InterimVar(InterimVar'high-1 downto 0) & DividendVar(loopVar); ResultVar(loopVar) := '0'; end if; end loop; -- round to the nearest digit if (InterimVar >= DivisorVal) then -- it the remainder is at least 1/2 of the Divisor (it was effectively multiplied by two during the final pass through the loop) ResultVar := ResultVar + '1'; -- then round up to the next value end if; return ResultVar(ResultVar'length-2 downto 0); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "/" -- -- DESCRIPTION : This function divides an unsigned std_logic_vector value -- by an integer value -- -- NOTES : -- ------------------------------------------------------------------------------ function "/"(DividendVal : std_logic_vector; DivisorVal : integer) return std_logic_vector is begin return DividendVal/int_to_slv(DivisorVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "/" -- -- DESCRIPTION : This function divides an integer string value -- by an integer value -- -- NOTES : -- ------------------------------------------------------------------------------ function "/"(DividendVal : string; DivisorVal : integer) return std_logic_vector is begin return strval_to_slv(DividendVal)/int_to_slv(DivisorVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bcd_to_led -- -- DESCRIPTION : This function converts a packed BCD vector or a hex value -- into a seven segment LED output -- -- NOTES if the CAVal boolean input is true the output will -- be for a Common Anode (1=off) display, otherwise it will -- be for a Common Cathode (1=on)display. -- _____ -- | a | -- f| |b -- |_____| -- | g | -- e| |c -- |_____| -- d -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to -- ------------------------------------------------------------------------------ function bcd_to_led(slvVal : std_logic_vector ; CAVal : boolean) return std_logic_vector is variable resultVar : std_logic_vector(7*slvVal'length/4-1 downto 0); variable vectorParseVar : std_logic_vector(3 downto 0); variable vectorVar : std_logic_vector(slvVal'length-1 downto 0); begin vectorVar := slvVal; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to for loopVar in 0 to slvVal'length/4-1 loop vectorParseVar := vectorVar(4*loopVar+3 downto 4*loopVar); case vectorParseVar is -- Illuminated -- vector Segment -- value abcdefg when x"0" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111110"; -- 0 when x"1" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110000"; -- 1 when x"2" => resultVar(7*loopVar+6 downto 7*loopvar) := "1101101"; -- 2 when x"3" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111001"; -- 3 when x"4" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110011"; -- 4 when x"5" => resultVar(7*loopVar+6 downto 7*loopvar) := "1011011"; -- 5 when x"6" => resultVar(7*loopVar+6 downto 7*loopvar) := "1011111"; -- 6 when x"7" => resultVar(7*loopVar+6 downto 7*loopvar) := "1110010"; -- 7 when x"8" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111111"; -- 8 when x"9" => resultVar(7*loopVar+6 downto 7*loopvar) := "1110011"; -- 9 when x"A" => resultVar(7*loopVar+6 downto 7*loopvar) := "0001000"; -- A when x"B" => resultVar(7*loopVar+6 downto 7*loopvar) := "1100000"; -- b when x"C" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110001"; -- C when x"D" => resultVar(7*loopVar+6 downto 7*loopvar) := "1000010"; -- d when x"E" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110000"; -- E when x"F" => resultVar(7*loopVar+6 downto 7*loopvar) := "0111000"; -- F when others => end case; end loop; if (CAVal) then return not resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to else return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bcd_to_slv -- -- DESCRIPTION : This function converts a packed binary coded decimal (BCD) -- in standard logic vector for and returns an unsigned, -- decending range, binary value -- -- NOTES -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector is type BCDArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector of std_logic_vector(vectorVal'length-1 downto 0); -- variable CarryVar : std_logic_vector(vectorVal'length/4 downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if no carry to the next BCD Digit is needed variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if carry to the next BCD Digit is needed variable BCDVar : BCDArrayType; -- BCD value array variable ResultVar : std_logic_vector(vectorVal'length-1 downto 0); begin BCDVar(0) := vectorVal; -- set the initial entry in the array to the input vector for OutrLoopVar in 1 to vectorVal'length loop -- CarryVar(CarryVar'high) := '0'; for InnrLoopVar in CarryVar'high-1 downto 0 loop -- start at the MSB of the BCD vector BCD_WoCarVar := '0' & BCDVar(OutrLoopVar-1) -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to (4*InnrLoopVar+3 downto 4*InnrLoopVar+1); -- read the results of the previous calculation BCD_WiCarVar := BCD_WoCarVar + "0101"; -- compute the result for the current BCD digit if carry is needed CarryVar(InnrLoopVar) := BCDVar(OutrLoopVar-1)(4*InnrLoopVar); -- read in the next bit of the LSB of the previous BCD digit input into the lowest carry bit if (CarryVar(InnrLoopVar+1) = '1') then -- if the the previous digit has a carry bit then then the result of the binary shift right is greater by 5 BCDVar(OutrLoopVar)(4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar; else -- otherwise BCDVar(OutrLoopVar)(4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar; -- we shift the bits right by 1 space end if; end loop; ResultVar(OutrLoopVar-1) := BCDVar(OutrLoopVar-1)(0); end loop; return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bcd_to_slv_pipe -- -- DESCRIPTION : This function converts a packed binary coded decimal (BCD) -- into an unsigned, decending range, -- binary value into a standard logic vector -- and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it. -- it is for use in pipelined implementations where -- the binary coded decimal output is registered -- and passed back to the function along with the binary -- vector input to be shifted out of its MSB -- register and into the function as a new bit. -- -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) ------------------------------------------------------------------------------ function bcd_to_slv_pipe( BCD_RVal : std_logic_vector; -- registered output of this function fed back in BCD_DigitsVal : integer) return std_logic_vector is -- binary coded decimal arithmetic shift right variable BCDVar : std_logic_vector(BCD_RVal'length-1 downto 0); variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0) := (others => '0'); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); variable BCD_WiCarVar : std_logic_vector(3 downto 0); variable ResultVar : std_logic_vector(4*BCD_DigitsVal-1 downto 0); begin BCDVar := BCD_RVal; CarryVar(CarryVar'high) := '0'; for loopVar in BCD_DigitsVal-1 downto 0 loop BCD_WoCarVar := '0' & BCDVar(4*loopVar+3 downto 4*loopVar+1); BCD_WiCarVar := BCD_WoCarVar + "0101"; CarryVar(loopVar) := BCDVar(4*loopVar); if (CarryVar(loopVar+1) = '1') then ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WiCarVar; else ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WoCarVar; end if; end loop; return ResultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bv_to_slv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an bit vector -- to a std logic vector. -- -- NOTES -- ------------------------------------------------------------------------------ function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector is begin return To_StdLogicVector(bitVectVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cdft (count down for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value (minus 2 for -- latency for counting down to an underflow for) using -- a string based frequency value, as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a variable -- value (CountValIn) for use with a counter styled similarly -- to this: -- -- CounterProcess  rocess(CountRSig,CountValIn)-- begin -- if (CountRSig(CountRSig'high) = '1') then -- CountSig <= CountValIn; -- PulseSig <= '1'; -- else -- CountSig <= CountRSig - 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cdft(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce((timeVar/freqStrVar) - 2); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cdft (count down for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value (minus 2 for -- latency for counting down to an underflow for) using -- a string based frequency (or period) value as a time -- base reference and a natural value for -- the length of the vector to return -- (if it will fit in a vector that size) -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a variable -- value (CountValIn) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig(CountRSig'high) = '1') then -- CountSig <= CountValIn; -- PulseSig <= '1'; -- else -- CountSig <= CountRSig - 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cdft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable lengthVar : natural; variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable zeroVar : std_logic_vector(natVal - cdfth(timeStrVal,freqStrVal) - 2 downto 0) := (others => '0'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); lengthVar := reduce_length((timeVar/freqStrVar) - 2); if (lengthVar >= natVal) then return reduce((timeVar/freqStrVar) - 2); else return zeroVar & reduce((timeVar/freqStrVar) - 2); end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cdfth (count down for time high) -- -- DESCRIPTION : This function computes the vector'high value -- from a string based time value (minus a count of 2 -- for use in counting down to underflow) and -- converts it to a std_logic_vector value using -- the a string based period value, as a reference -- This function requires units in each string -- -- NOTES -- ------------------------------------------------------------------------------ function cdfth(timeStrVal : string; freqStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_high((timeVar/freqStrVar) - 2); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : ceil -- -- DESCRIPTION : This function rounds a real value up to the next -- real integer -- -- NOTES -- ------------------------------------------------------------------------------ function ceil (RealVal : in real) return real is constant integerMaxVal : real := real(integer'high); variable RoundVar : real; variable ResultVar : real; begin RoundVar := real(integer(RealVal)); if (abs(RealVal) >= integerMaxVal) then ResultVar := RealVal; elsif (RoundVar = RealVal) then ResultVar := RoundVar; elsif (RealVal > 0.0) then if (RoundVar >= RealVal) then ResultVar := RoundVar; else ResultVar := RoundVar + 1.0; end if; elsif (RealVal = 0.0) then ResultVar := 0.0; else if (RoundVar <= RealVal) then ResultVar := RoundVar + 1.0; else ResultVar := RoundVar; end if; end if; return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cfi (characters for integer) -- -- DESCRIPTION : This function returns a natural representing the -- number of characters required to reprsent an -- integer value. It is essentially -- an integer'length function for the characters. -- -- NOTES : -- ------------------------------------------------------------------------------ function cfi(intVal : integer) return natural is variable intVar : integer; variable negVar : boolean; begin if (intVal < 0) then intVar := -intVal; negVar := true; else intVar := intVal; negVar := false; end if; for LoopVar in 1 to MAX_VECT_SIZE loop if (intVar = 0) then return 1; elsif (intVar < 10 and intVar >= 1) then if (negVar) then return loopVar + 1; -- allow for the '-' character else return loopVar; end if; else intVar := intVar/10; end if; end loop; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cft (count for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference. -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cft(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce(timeVar/freqStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cft (count for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency (or period) value as a time -- base reference and a natural value for -- the length of the vector to return -- (if it will fit in a vector that size) -- This function requires units in each string -- -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable lengthVar : natural; variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable zeroVar : std_logic_vector(natVal - cfth(timeStrVal,freqStrVal) - 2 downto 0) := (others => '0'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); lengthVar := reduce_length(timeVar/freqStrVar); if (lengthVar >= natVal) then return reduce(timeVar/freqStrVar); else return zeroVar & reduce(timeVar/freqStrVar); end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cfth (count for time high) -- -- DESCRIPTION : This function computes the vector'high value -- from a string based time value using -- the a string based frequency (or period) -- value, as a reference -- This function requires units in each string -- -- NOTES -- ------------------------------------------------------------------------------ function cfth(timeStrVal : string; freqStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_high(timeVar/freqStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cftu (count for time unsigned) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cftu(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_unsigned(timeVar/freqStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cftu (count for time unsigned) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cftu(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable fudgeStrVar : integer; begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); fudgeStrVar := str_to_int(fudgeStrVal); return reduce_unsigned(timeVar/freqStrVar + fudgeStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : clkcnt (50% duty cycle clock count) -- -- DESCRIPTION : This function takes a string based frequency value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference -- NOTES -- this function is for use with a process which counts -- up to a static value. This method tends to give the smallest and -- fastest circuit -- --CounterProcess2 rocess(ClkRSig,Count2RSig)-- variable CLKCNTVAL : std_logic_vector := clkcnt("Freq1StrVal","Freq2StrVal") --begin -- if (Count2RSig = CLKCNTVAL) then -- Count2Sig <= (others => '0'); -- ClkSig <= not ClkRSig; -- else -- Count2Sig <= Count2RSig + 1; -- ClkSig <= ClkRSig; -- end if; --end process; -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function clkcnt(freq1StrVal : string; freq2StrVal : string) return std_logic_vector is variable freq1StrVar : std_logic_vector(strval_to_slv_var_base_high(freq1 StrVal,CFT_BASE_SIZE) downto 0); variable freq2StrVar : std_logic_vector(strval_to_slv_var_base_high(freq2 StrVal,CFT_BASE_SIZE) downto 0); begin freq1StrVar := strval_to_slv(freq1StrVal,CFT_BASE_SIZE); freq2StrVar := strval_to_slv(freq2StrVal,CFT_BASE_SIZE); return reduce_unsigned((freq1StrVar/freq2StrVar)/2-1); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : conv_to_hex -- -- DESCRIPTION : This function converts a bit vector of any length to a -- string representing the Hexadecimal value of that vector -- NOTES -- ------------------------------------------------------------------------------ function conv_to_hex(vectorVal : bit_vector) return string is variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1); variable vectorParseVar : std_logic_vector(4 downto 1); variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'leng th)/4.0)))*4 downto 1); variable VectorVar : bit_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; vectorStretchVar := ext(to_stdlogicvector(VectorVar),vectorStretchVar' length); for loopVar in resultVar'range loop vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-3); case vectorParseVar(4 downto 1) is when x"0" => resultVar(loopVar) := '0'; when x"1" => resultVar(loopVar) := '1'; when x"2" => resultVar(loopVar) := '2'; when x"3" => resultVar(loopVar) := '3'; when x"4" => resultVar(loopVar) := '4'; when x"5" => resultVar(loopVar) := '5'; when x"6" => resultVar(loopVar) := '6'; when x"7" => resultVar(loopVar) := '7'; when x"8" => resultVar(loopVar) := '8'; when x"9" => resultVar(loopVar) := '9'; when x"A" => resultVar(loopVar) := 'A'; when x"B" => resultVar(loopVar) := 'B'; when x"C" => resultVar(loopVar) := 'C'; when x"D" => resultVar(loopVar) := 'D'; when x"E" => resultVar(loopVar) := 'E'; when x"F" => resultVar(loopVar) := 'F'; when others => end case; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : conv_to_hex -- -- DESCRIPTION : This function converts a logic vector of any length to a -- string representing the Hexadecimal value of that vector -- NOTES -- ------------------------------------------------------------------------------ function conv_to_hex(vectorVal : std_logic_vector) return string is variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1); variable vectorParseVar : std_logic_vector(4 downto 1); variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'leng th)/4.0)))*4 downto 1); variable VectorVar : std_logic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; vectorStretchVar := ext(VectorVar,vectorStretchVar'length); for loopVar in resultVar'range loop vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-3); case vectorParseVar(4 downto 1) is when x"0" => resultVar(loopVar) := '0'; when x"1" => resultVar(loopVar) := '1'; when x"2" => resultVar(loopVar) := '2'; when x"3" => resultVar(loopVar) := '3'; when x"4" => resultVar(loopVar) := '4'; when x"5" => resultVar(loopVar) := '5'; when x"6" => resultVar(loopVar) := '6'; when x"7" => resultVar(loopVar) := '7'; when x"8" => resultVar(loopVar) := '8'; when x"9" => resultVar(loopVar) := '9'; when x"A" => resultVar(loopVar) := 'A'; when x"B" => resultVar(loopVar) := 'B'; when x"C" => resultVar(loopVar) := 'C'; when x"D" => resultVar(loopVar) := 'D'; when x"E" => resultVar(loopVar) := 'E'; when x"F" => resultVar(loopVar) := 'F'; when others => end case; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : conv_to_hex -- -- DESCRIPTION : This function converts a ulogic vector of any length to a -- string representing the Hexadecimal value of that vector -- NOTES -- ------------------------------------------------------------------------------ function conv_to_hex(vectorVal : std_ulogic_vector) return string is variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1); variable vectorParseVar : std_logic_vector(4 downto 1); variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'leng th)/4.0)))*4 downto 1); variable VectorVar : std_ulogic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; vectorStretchVar := ext(to_stdlogicvector(VectorVar),vectorStretchVar' length); for loopVar in resultVar'range loop vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-3); case vectorParseVar(4 downto 1) is when x"0" => resultVar(loopVar) := '0'; when x"1" => resultVar(loopVar) := '1'; when x"2" => resultVar(loopVar) := '2'; when x"3" => resultVar(loopVar) := '3'; when x"4" => resultVar(loopVar) := '4'; when x"5" => resultVar(loopVar) := '5'; when x"6" => resultVar(loopVar) := '6'; when x"7" => resultVar(loopVar) := '7'; when x"8" => resultVar(loopVar) := '8'; when x"9" => resultVar(loopVar) := '9'; when x"A" => resultVar(loopVar) := 'A'; when x"B" => resultVar(loopVar) := 'B'; when x"C" => resultVar(loopVar) := 'C'; when x"D" => resultVar(loopVar) := 'D'; when x"E" => resultVar(loopVar) := 'E'; when x"F" => resultVar(loopVar) := 'F'; when others => end case; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : crc16 -- -- DESCRIPTION : returns the input to a Cyclic Redundancy Check (CRC) -- using the polynomial x^16 + x^15 + x^2 + 1 -- (CRC-16-CCITT) -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- -- http://en.wikipedia.org/wiki/LFSR ------------------------------------------------------------------------------ function crc16(serialInVal : std_logic; vectorVal : std_logic_vector) return std_logic_vector is -- constant OUTPUT_FILE : string := LOG_PATH & "crc16_function_logfile" & LOG_EXT; -- variable LogFileLine : line; -- file LogFile : text open write_mode is OUTPUT_FILE; variable vector1Var : std_logic_vector(1 to 16); -- CRCs are usually depicted shifting left to right with the right being the MSB variable vector2Var : std_logic_vector(1 to 16); -- CRCs are usually depicted shifting left to right with the right being the MSB begin vector1Var := vectorVal; vector2Var := '0' & vector1Var(1 to 15); -- default to vector1Var shifted right vector2var(1) := serialInVal xor vector1Var(15); vector2Var(3) := serialInVal xor vector1Var(2) xor vector1Var(16); vector2Var(16) := serialInVal xor vector1Var(15) xor vector1Var(16); return vector2Var; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cslv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an integer (int1Val) -- to a std logic vector of length int2Val. -- -- NOTES -- ------------------------------------------------------------------------------ function cslv(int1Val : integer; int2Val : integer) return std_logic_vector is begin return conv_std_logic_vector(int1Val,int2Val); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cslv (convert signed to std_logic_vector) -- -- DESCRIPTION : This function converts an signed value -- to a std logic vector of length intVal. -- -- NOTES -- ------------------------------------------------------------------------------ function cslv(sigVal : signed; intVal : integer) return std_logic_vector is begin return conv_std_logic_vector(sigVal,intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cslv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an unsigned value -- to a std logic vector of length intVal. -- -- NOTES -- ------------------------------------------------------------------------------ function cslv(usgVal : unsigned; intVal : integer) return std_logic_vector is begin return conv_std_logic_vector(usgVal,intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cuft (count up for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector (minus one for latency) -- value using a string based frequency (or period) value, -- as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a constant -- value (COUNTVALUE) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig = COUNTVALUE) then -- CountSig <= (others => '0'); -- PulseSig <= '1'; -- else -- CountSig <= CountRSig + 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cuft(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_unsigned((timeVar/freqStrVar) - 1); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cuft (count up for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector (minus one for latency) -- value using a string based frequency (or period) value -- as a time base reference and a natural value for -- the length of the vector to return -- (if it will fit in a vector that size) -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to: -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a constant -- value (COUNTVALUE) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig = COUNTVALUE) then -- CountSig <= (others => '0'); -- PulseSig <= '1'; -- else -- CountSig <= CountRSig + 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cuft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable lengthVar : natural; variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable zeroVar : std_logic_vector(natVal - cufth(timeStrVal,freqStrVal) - 2 downto 0) := (others => '0'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); lengthVar := reduce_length_unsigned((timeVar/freqStrVar) - 1); if (lengthVar >= natVal) then return reduce_unsigned((timeVar/freqStrVar) - 1); else return zeroVar & reduce_unsigned((timeVar/freqStrVar) - 1); end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cufth (count up for time high) -- -- DESCRIPTION : This function computes the vector'high value -- from a string based time value (minus a count of 1 -- for use in counting up from zero to the proper value) using -- the a string based period value, as a reference -- This function requires units in each string -- -- NOTES -- ------------------------------------------------------------------------------ function cufth(timeStrVal : string; freqStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_high_unsigned((timeVar/freqStrVar) - 1); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfi (decimal places for integer) -- -- DESCRIPTION : This function returns a natural representing the -- number of digits in an integer value. It is essentially -- an integer'length function (does not count -- a '-' character). -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfi(intVal : integer) return natural is variable intVar : integer; variable CountVar : natural := 1; variable ResultVar : natural; begin if (intVal < 0) then intVar := -intVal; else intVar := intVal; end if; for CountVar in 1 to MAX_VECT_SIZE loop if (intVal = 0) then return 1; elsif (intVar < 10 and intVar >= 1) then return CountVar; else intVar := intVar/10; end if; end loop; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfi_syn (decimal places for integer (synthesizeable)) -- -- DESCRIPTION : This function returns a natural representing the -- number of digits in an integer value. It is essentially -- an integer'length function. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfi_syn(intVal : integer) return natural is variable resultVar : natural; begin if (intVal <= -1_000_000_000 or intVal >= 1_000_000_000) then resultVar := 10; elsif (intVal <= -100_000_000 or intVal >= 100_000_000) then resultVar := 9; elsif (intVal <= -10_000_000 or intVal >= 10_000_000) then resultVar := 8; elsif (intVal <= -1_000_000 or intVal >= 1_000_000) then resultVar := 7; elsif (intVal <= -100_000 or intVal >= 100_000) then resultVar := 6; elsif (intVal <= -10_000 or intVal >= 10_000) then resultVar := 5; elsif (intVal <= -1_000 or intVal >= 1_000) then resultVar := 4; elsif (intVal <= -100 or intVal >= 100) then resultVar := 3; elsif (intVal <= -10 or intVal >= 10) then resultVar := 2; else resultVar := 1; end if; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfr (decimal places for real) -- -- DESCRIPTION : This function returns a natural value representing the -- number of digits to the left of the decimal -- in a real value. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfr(realVal : real) return natural is variable realVar : real; variable ResultVar : natural; begin if (realVal < 0.0) then realVar := -realVal; else realVar := realVal; end if; for loopVar in 1 to MAX_VECT_SIZE loop if (realVal = 0.0) then return 1; elsif (realVar < 10.0 and realVar >= 1.0) then return loopVar; else realVar := realVar/10.0; end if; end loop; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfslvr (decimal places for slv range) -- -- DESCRIPTION : This function returns a natural representing the -- number of decimal places the largest integer value that -- can be represented by a vector will occupy. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfslvr(vectorVal : std_logic_vector) return natural is variable returnVar : std_logic_vector(vectorVal'length-1 downto 0) := (others => '1'); begin return dpfi(conv_integer(returnVar)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfslvv (decimal places for slv value) -- -- DESCRIPTION : This function returns a natural representing the -- number of decimal places the integer value represented -- by a vector will occupy. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfslvv(vectorVal : std_logic_vector) return natural is begin return dpfi(conv_integer(vectorVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : eq -- -- DESCRIPTION : This function is an equality check function -- that is sensitive to vector length -- NOTES -- ------------------------------------------------------------------------------ function eq(vector1Val : std_logic_vector; vector2Val : std_logic_vector) return boolean is variable sl1Var : std_logic; variable sl2Var : std_logic; variable resultVar : boolean; variable vector1Var : std_logic_vector(vector1Val'length-1 downto 0); variable vector2Var : std_logic_vector(vector2Val'length-1 downto 0); begin resultVar := true; vector1Var := vector1Val; vector2Var := vector2Val; if (vector1Var'high /= vector2Var'high) then -- check for length mismatch return false; end if; for loopVar in vector1Var'range loop if (vector1Var(loopVar) /= vector2Var(loopVar)) then resultVar := false; end if; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : ext (space extend) -- -- DESCRIPTION : This function returns a string, -- padded with spaces, to the length specified by natVal -- -- NOTES : -- ------------------------------------------------------------------------------ function ext(strVal : string; natVal : natural) return string is variable resultVar : string(1 to natVal); variable strVar : string(1 to strVal'length); variable spaceVar : string(1 to max(natVal-strVal'length,1)); begin strVar := strVal; if (strVal'length >= natVal) then return strVal; else for loopVar in spaceVar'range loop spaceVar(loopVar) := ' '; -- fill with spaces end loop; end if; resultVar := spaceVar & strVar; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : ext2 (zero extend) -- -- DESCRIPTION : This function returns a standard logic vector, -- padded with zeros, to the length specified by natVal -- -- NOTES : -- ------------------------------------------------------------------------------ function ext2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector is variable vectorVar : std_logic_vector (vectorVal'length - 1 downto 0); variable zeroVar : std_logic_vector (natVal - vectorVal'length - 1 downto 0) := (others => '0'); begin vectorVar := vectorVal; if (vectorVar'length >= natVal) then return vectorVar; else return zeroVar & vectorVar; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : flip -- -- DESCRIPTION : This function returns a vector with all the bits -- in the vector flipped. -- i.e. if vectorval = 00011001 -- flip(vectorval) returns 10011000 -- NOTES -- ------------------------------------------------------------------------------ function flip(vectorVal : bit_vector) return bit_vector is variable resultVar : bit_vector(vectorVal'range); begin for loopVar in vectorVal'range loop resultVar(resultVar'high-loopVar) := vectorVal(loopVar); end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : flip -- -- DESCRIPTION : This function returns a vector with all the bits -- in the vector flipped. -- i.e. if vectorval = 00011001 -- flip(vectorval) returns 10011000 -- NOTES -- ------------------------------------------------------------------------------ function flip(vectorVal : std_logic_vector) return std_logic_vector is variable resultVar : std_logic_vector(vectorVal'range); begin for loopVar in vectorVal'range loop resultVar(resultVar'high-loopVar) := vectorVal(loopVar); end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : flip -- -- DESCRIPTION : This function returns a vector with all the bits -- in the vector flipped. -- i.e. if vectorval = 00011001 -- flip(vectorval) returns 10011000 -- NOTES -- ------------------------------------------------------------------------------ function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector is variable resultVar : std_ulogic_vector(vectorVal'range); begin for loopVar in vectorVal'range loop resultVar(resultVar'high-loopVar) := vectorVal(loopVar); end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : floor -- -- DESCRIPTION : This function rounds a real value down to the next -- real integer -- -- NOTES -- ------------------------------------------------------------------------------ function floor(RealVal : in real) return real is constant integerMaxVal : real := real(integer'high); variable RoundVar : real; variable ResultVar : real; begin RoundVar := real(integer(RealVal)); -- eliminate all the digits after the decimal point if (abs(RealVal) >= integerMaxVal) then -- if the real value is larger than the maximum integer value then we can't continue ResultVar := RealVal; elsif (RoundVar = RealVal) then -- if it's equal then return the same value ResultVar := RoundVar; elsif (RealVal > 0.0) then -- if its greater then 0.0 it's positve so we return the less postive number if (RoundVar >= RealVal) then ResultVar := RoundVar - 1.0; else ResultVar := RoundVar; end if; elsif (RealVal = 0.0) then -- if it's 0.0 then return 0.0 ResultVar := 0.0; else if (RoundVar <= RealVal) then -- if its less then 0.0 it's negative so we return the more negative number ResultVar := RoundVar; else ResultVar := RoundVar - 1.0; end if; end if; return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : hex_to_slv -- -- DESCRIPTION : This function converts a Hexadecimal value string -- of any length to a std_logic_vector -- -- NOTES -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function hex_to_slv(stringVal : string) return std_logic_vector is variable stringVar : string(1 to stringVal'length); variable resultVar : std_logic_vector(4*stringVal'length downto 1); variable vectorParseVar : character; begin stringVar := stringVal; for loopVar in stringVar'range loop vectorParseVar := stringVar(loopVar); case vectorParseVar is when '0' => resultVar(4*loopVar downto 4*loopvar-3) := x"0"; when '1' => resultVar(4*loopVar downto 4*loopvar-3) := x"1"; when '2' => resultVar(4*loopVar downto 4*loopvar-3) := x"2"; when '3' => resultVar(4*loopVar downto 4*loopvar-3) := x"3"; when '4' => resultVar(4*loopVar downto 4*loopvar-3) := x"4"; when '5' => resultVar(4*loopVar downto 4*loopvar-3) := x"5"; when '6' => resultVar(4*loopVar downto 4*loopvar-3) := x"6"; when '7' => resultVar(4*loopVar downto 4*loopvar-3) := x"7"; when '8' => resultVar(4*loopVar downto 4*loopvar-3) := x"8"; when '9' => resultVar(4*loopVar downto 4*loopvar-3) := x"9"; when 'a' | 'A' => resultVar(4*loopVar downto 4*loopvar-3) := x"A"; when 'b' | 'B' => resultVar(4*loopVar downto 4*loopvar-3) := x"B"; when 'c' | 'C' => resultVar(4*loopVar downto 4*loopvar-3) := x"C"; when 'd' | 'D' => resultVar(4*loopVar downto 4*loopvar-3) := x"D"; when 'e' | 'E' => resultVar(4*loopVar downto 4*loopvar-3) := x"E"; when 'f' | 'F' => resultVar(4*loopVar downto 4*loopvar-3) := x"F"; when others => end case; end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : int_to_slv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an integer value to a -- std_logic_vector with a range just large enough -- to represent it -- -- NOTES -- ------------------------------------------------------------------------------ function int_to_slv(intVal : integer) return std_logic_vector is begin return conv_std_logic_vector(intVal,vlfi(intVal)); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : itoa -- -- DESCRIPTION : commonly used integer-to-string type converter -- -- NOTES -- ------------------------------------------------------------------------------ --function itoa(intVal : integer) return string is -- variable IntVar : integer := intVal; --begin -- if (IntVar < 0) then -- return "-" & itoa(-IntVar); -- elsif IntVar < 10 then -- return IntString(IntVar); -- else -- return itoa(IntVar/10) & IntString(IntVar rem 10); -- end if; --end function itoa; function itoa(intVal : integer) return string is begin return to_string(intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr (Linear Feedback Shift Register) -- -- DESCRIPTION : returns the input for the next cycle of a -- Linear Feedback Shift Register (LFSR) -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- ------------------------------------------------------------------------------ function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string; polynomialStrVal : string) return std_logic_vector is type termArrayType is array (1 to 20) of integer; -- supports up to 20 terms in a polynomial constant polynomialConst : string := polynomialStrVal; -- holds the string containing the exponent values (from highest to lowest power, separated by commas or + signs) variable seperatorLocationVar : integer; -- marks the location of the last exponent seperator variable polynomialParseVar : character; -- character value used to index through the polynomialVar string to look for seperators variable tapFoundVar : boolean; variable termArray : termArrayType; variable termQtyVar : integer; -- used to determine the number of terms in the polynomial variable type2Var : boolean; variable typeParseVar : character; variable typeVar : string(1 to lfsrTypeVal'length); variable typeXORVar : boolean; variable vector1Var : std_logic_vector(1 to vectorVal'length); -- LFSRs are usually depicted shifting left to right with the right being the MSB variable vector2Var : std_logic_vector(1 to vectorVal'length); -- LFSRs are usually depicted shifting left to right with the right being the MSB begin seperatorLocationVar := 1; tapFoundVar := FALSE; for loopVar in termArray'range loop termArray(loopVar) := 0; -- initialize to 0s end loop; termQtyVar := 1; type2Var := TRUE; typeVar := lfsrTypeVal; typeXORVar := TRUE; vector1Var := vectorVal; vector2Var := vector1Var; polynomial_string_parser : for loopVar in polynomialConst'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found polynomialParseVar := polynomialConst(loopVar); if (polynomialParseVar = ',' or polynomialParseVar = '+') then termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; termQtyVar := termQtyVar + 1; elsif (loopVar = polynomialConst'high) then -- this is the last term termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; end if; end loop polynomial_string_parser; type_string_parser : for loopVar in typeVar'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found typeParseVar := typeVar(loopVar); if (typeParseVar = 'n' or typeParseVar = 'N') then -- if there is an n or N present it must be an XNOR type feedback typeXORVar := FALSE; elsif (typeParseVar = '1') then -- if there is an 1 present it must be type 1 feedback type2Var := FALSE; end if; end loop type_string_parser; if (not type2Var) then -- Type 1 feedback (Fibonacci) (many output to one input) if (not typeXORVar) then vector2Var(vector2Var'low) := '1'; for loopVar in 1 to termQtyVar loop -- this loop determines the next input value for a Type 1 LFSR vector2Var(vector2Var'low) := not (vector1Var(termArray(loopVar)) xor vector2Var(vector2Var'low)); end loop; vector2Var := vector2Var(vector2Var'low) & vector1Var(vector1Var'low to vector1Var'high-1); else vector2Var(vector2Var'low) := '0'; for loopVar in 1 to termQtyVar loop -- this loop determines the next input value for a Type 1 LFSR vector2Var(vector2Var'low) := vector1Var(termArray(loopVar)) xor vector2Var(vector2Var'low); end loop; vector2Var := vector2Var(vector2Var'low) & vector1Var(vector1Var'low to vector1Var'high-1); end if; else -- Type 2 feedback (Galois) (one output to many inputs) if (not typeXORVar) then vector2var(vector2var'low) := vector1Var(vector1Var'high); -- highest power term alway wraps around to the input for outrLoopVar in 2 to vector2Var'high loop -- this loop determines the next value for the LFSR tapFoundVar := FALSE; for innrLoopVar in 2 to termQtyVar loop -- highest power term (termArray(1)) isn't needed below if (termArray(innrLoopVar) = outrLoopVar-1) then tapFoundVar := TRUE; vector2Var(outrLoopVar) := not (vector1Var(outrLoopVar-1) xor vector1Var(vector1Var'high)); -- xor in where a tap should be elsif (not tapFoundVar) then vector2Var(outrLoopVar) := vector1Var(outrLoopVar-1); -- if there's no tap then get the previous registers value end if; end loop; end loop; else vector2var(vector2var'low) := vector1Var(vector1Var'high); -- highest power term alway wraps around to the input for outrLoopVar in 2 to vector2Var'high loop -- this loop determines the next value for the LFSR tapFoundVar := FALSE; for innrLoopVar in 2 to termQtyVar loop -- highest power term (termArray(1)) isn't needed below if (termArray(innrLoopVar) = outrLoopVar-1) then tapFoundVar := TRUE; vector2Var(outrLoopVar) := vector1Var(outrLoopVar-1) xor vector1Var(vector1Var'high); -- xor in where a tap should be elsif (not tapFoundVar) then vector2Var(outrLoopVar) := vector1Var(outrLoopVar-1); -- if there's no tap then get the previous registers value end if; end loop; end loop; end if; end if; return vector2Var; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr -- -- DESCRIPTION : returns the input for the next cycle of a -- Linear Feedback Shift Register (LFSR) -- using a primitive polynomial -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- ------------------------------------------------------------------------------ function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string) return std_logic_vector is begin return lfsr(vectorVal,lfsrTypeVal,LFSR_Polynomial_Exponen ts(vectorVal'length)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr -- -- DESCRIPTION : returns the input for the next cycle of a -- Linear Feedback Shift Register (LFSR) -- using a primitive polynomial. This version uses -- a Type 2 XOR feedback structure -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- ------------------------------------------------------------------------------ function lfsr(vectorVal : std_logic_vector) return std_logic_vector is begin return lfsr(vectorVal,"Type 2 xor",LFSR_Polynomial_Exponents(vectorVal'length)) ; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft -- -- DESCRIPTION : returns the value a Linear Feedback Shift Register -- (LFSR) will contain after the amount -- of time specified using the frequency (or period) -- value passed as a reference and the seed value -- passed as a starting point -- -- NOTES : this function will probably run slowly when used for synthesis -- ------------------------------------------------------------------------------ function lfsr_cft(timeStrVal : string; freqStrVal : string; seedVal : std_logic_vector; lfsrTypeVal : string; fudgeStrVal : string) return std_logic_vector is -- synopsys translate_off constant OUTPUT_FILE : string := LOG_PATH & "lfsr_cft_function_logfile" & LOG_EXT; variable LogFileLine : line; file LogFile : text; --open append_mode is OUTPUT_FILE; -- synopsys translate_on type termArrayType is array (1 to 20) of integer; -- supports up to 20 terms in a polynomial constant high : integer := lfsr_cfth(timeStrVal,freqStrVal,fudgeStrVal); constant length : integer := high+1; constant lowerBound : integer := LFSRLowerBound; constant upperBound : integer := LFSRUpperBound; constant polynomialConst : string := LFSR_Polynomial_Exponents(length); -- holds the string containing the exponent values (from highest to lowest power, separated by commas or + signs) variable countDoneVar : std_logic_vector(high downto 0) := ext(cftu(timeStrVal,freqStrVal,fudgeStrVal),length ); -- stop value for counter used to determine when the loop which computes the lfsr stop value should stop looping variable countVar : std_logic_vector(high downto 0) := (others => '0'); -- counter counter used to determine when the loop which computes the lfsr stop value should stop looping variable fudgeVar : string(1 to fudgeStrVal'length) := fudgeStrVal; -- shift the count by the number indicated variable lfsr_strIndexVar : integer := 0; variable loopEnableVar : boolean := TRUE; variable polynomialParseVar : character; -- character value used to index through the polynomialVar string to look for seperators variable seedVar : std_logic_vector(high downto 0) := ext(seedVal,length); variable seperatorLocationVar : integer := 1; -- marks the location of the last exponent seperator variable stopVar : std_logic_vector(high downto 0) := (others => '1'); variable tapFoundVar : boolean := FALSE; variable termArray : termArrayType; variable termQtyVar : integer := 1; -- used to determine the number of terms in the polynomial variable type2FBVar : boolean := TRUE; variable typeParseVar : character; variable typeSimLoopVar : boolean := TRUE; variable typeVar : string(1 to lfsrTypeVal'length) := lfsrTypeVal; variable typeXORVar : boolean := TRUE; variable vector1Var : std_logic_vector(1 to length) := seedVar; -- LFSRs are usually depicted shifting left to right with the right being the MSB variable vector2Var : std_logic_vector(1 to length) := seedVar; -- LFSRs are usually depicted shifting left to right with the right being the MSB variable xorMaskVar : std_logic_vector(1 to length) := (others => '0'); -- holds the xor feedback variable begin -- synopsys translate_off file_open(LogFile, OUTPUT_FILE, append_mode); -- synopsys translate_on for loopVar in lowerBound to length-1 loop lfsr_strIndexVar := 2**loopVar-1 + lfsr_strIndexVar; end loop; lfsr_strIndexVar := lfsr_strIndexVar + to_int(countDoneVar) + 1; array_initializer : for loopVar in termArray'range loop termArray(loopVar) := 0; -- initialize to 0s end loop array_initializer; polynomial_string_parser : for loopVar in polynomialConst'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found polynomialParseVar := polynomialConst(loopVar); if (polynomialParseVar = ',' or polynomialParseVar = '+') then -- commas or '+' signs can be used as seperators for the exponents termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; termQtyVar := termQtyVar + 1; elsif (loopVar = polynomialConst'high) then -- this is the last term termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; end if; end loop polynomial_string_parser; xor_vector_computer : for outrLoopVar in xorMaskVar'range loop -- compute the value that the xor vector should have to make an LFSR with a given polynomial for innrLoopVar in 1 to termQtyVar loop if (termArray(innrLoopVar) = outrLoopVar) then xorMaskVar(outrLoopVar) := '1'; end if; end loop; end loop xor_vector_computer; type_string_parser : for loopVar in typeVar'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found typeParseVar := typeVar(loopVar); if (typeParseVar = 'n' or typeParseVar = 'N') then -- if there is an n or N present it must be an XNOR type feedback typeXORVar := FALSE; elsif (typeParseVar = '1') then -- if there is an 1 present it must be type 1 feedback type2FBVar := FALSE; elsif (typeParseVar = 's' or typeParseVar = 'S') then if (typeVar(loopVar+1) = 'y' or typeVar(loopVar+1) = 'Y') then typeSimLoopVar := FALSE; -- this function call must be for synthesis end if; end if; end loop type_string_parser; if typeSimLoopVar then if (not type2FBVar) then -- Type 1 feedback (Fibonacci) (many output to one input) if (not typeXORVar) then type1_xnor_stop_value_computer : while loopEnableVar loop if loopEnableVar then countVar := countVar + 1; vector2Var := xnor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type1_xnor_stop_value_computer; else type1_xor_stop_value_computer : while loopEnableVar loop if loopEnableVar then countVar := countVar + 1; vector2Var := xor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type1_xor_stop_value_computer; end if; else -- Type 2 feedback (Galois) (one output to many inputs) if (not typeXORVar) then xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); type2_xnor_stop_value_computer : while loopEnableVar loop if (vector1Var(vector1Var'high) = '1' and loopEnableVar) then countVar := countVar + 1; vector2Var := not ((vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor not(xorMaskVar)); -- shift right and apply xnor vector1Var := vector2Var; elsif (loopEnableVar) then countVar := countVar + 1; vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type2_xnor_stop_value_computer; else xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); type2_xor_stop_value_computer : while loopEnableVar loop if (vector1Var(vector1Var'high) = '1' and loopEnableVar) then countVar := countVar + 1; vector2Var := (vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor xorMaskVar; -- shift right and apply xor vector1Var := vector2Var; elsif (loopEnableVar) then countVar := countVar + 1; vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type2_xor_stop_value_computer; end if; end if; else -- synthesis oriented version below (no while loops that the synthesis tool struggles with) if (not type2FBVar) then -- Type 1 feedback (Fibonacci) (many output to one input) if (not typeXORVar) then syn_type1_xnor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop vector2Var := xnor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end loop syn_type1_xnor_stop_value_computer; else syn_type1_xor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop vector2Var := xor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end loop syn_type1_xor_stop_value_computer; end if; else -- Type 2 feedback (Galois) (one output to many inputs) if (not typeXORVar) then xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); syn_type2_xnor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop if (vector1Var(vector1Var'high) = '1') then vector2Var := not ((vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor not(xorMaskVar)); -- shift right and apply xnor vector1Var := vector2Var; else vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; end loop syn_type2_xnor_stop_value_computer; else --vector2Var := str_to_slv(lfsr_str(lfsr_strIndexVar)); xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); syn_type2_xor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop if (vector1Var(vector1Var'high) = '1') then vector2Var := (vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor not(xorMaskVar); -- shift right and apply xor vector1Var := vector2Var; else vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; end loop syn_type2_xor_stop_value_computer; end if; end if; end if; stopVar := vector2Var; -- synopsys translate_off write(LogFileLine, LF & "polynomialConst : " & to_string(lfsr_cfth(timeStrVal,freqStrVal,fudgeStr Val)+1) & LF & "exponent values : " & polynomialConst & LF & "xorMaskVar value : " & to_string(xorMaskVar) & LF & "LFSR count time : " & timeStrVal & LF & "reference time/period : " & freqStrVal & LF & "fudge factor : " & fudgeStrVal & LF & "type2FBVar : " & to_string(type2FBVar) & LF & "typeXORVar : " & to_string(typeXORVar) & LF & "# of clock cycles : " & to_string(to_int(countDoneVar)) & LF & "LFSR length : " & to_string(stopVar'length) & LF & "LFSR stop value : " & to_string(stopVar) & LF & LF ); writeLine(LogFile,LogFileLine); assert FALSE report LF & "polynomialConst : " & to_string(lfsr_cfth(timeStrVal,freqStrVal,fudgeStr Val)+1) & LF & "exponent values : " & polynomialConst & LF & "xorMaskVar value : " & to_string(xorMaskVar) & LF & "LFSR count time : " & timeStrVal & LF & "reference time/period : " & freqStrVal & LF & "fudge factor : " & fudgeStrVal & LF & "type2FBVar : " & to_string(type2FBVar) & LF & "typeXORVar : " & to_string(typeXORVar) & LF & "# of clock cycles : " & to_string(to_int(countDoneVar)) & LF & "LFSR length : " & to_string(stopVar'length) & LF & "LFSR stop value : " & to_string(stopVar) & LF & LF severity note; file_close(LogFile); -- synopsys translate_on return stopVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector is constant seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal,f udgeStrVal) downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor",fudgeStrVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft(timeStrVal : string; freqStrVal : string) return std_logic_vector is constant seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor","0"); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft_piped -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft_piped(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor",pipelined_comparator_latency(timeStrVal,freqS trVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft_piped_syn -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft_piped_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor syn",pipelined_comparator_latency(timeStrVal,freqS trVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft_syn -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor syn","0"); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cfth -- -- DESCRIPTION : -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cfth(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0) := strval_to_slv(freqStrVal,CFT_BASE_SIZE); variable timeStrVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0) := strval_to_slv(timeStrVal,CFT_BASE_SIZE); variable fudgeStrVar : integer := str_to_int(fudgeStrVal); variable resultVar : integer := reduce_high_unsigned(timeStrVar/freqStrVar + fudgeStrVar); variable onesVar : std_logic_vector(resultVar downto 0) := (others => '1'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeStrVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); fudgeStrVar := str_to_int(fudgeStrVal); resultVar := reduce_high_unsigned(timeStrVar/freqStrVar + fudgeStrVar); if (timeStrVar/freqStrVar + fudgeStrVar = onesVar) then resultVar := resultVar + 1; end if; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cfth -- -- DESCRIPTION : -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cfth(timeStrVal : string; freqStrVal : string) return integer is begin return lfsr_cfth(timeStrVal,freqStrVal,"0"); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : max -- -- DESCRIPTION : This function returns the greater of the two values -- passed. -- -- NOTES : ------------------------------------------------------------------------------ function max(int1Val : integer; int2Val : integer) return integer is begin if (int1Val > int2Val) then return int1Val; else return int2Val; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : mult_s -- -- DESCRIPTION : This function multiplies a signed std_logic vector -- value by another signed std_logic_vector value -- -- NOTES : This function is provided for in std_logic_arith ------------------------------------------------------------------------------ function mult_s(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector is variable negVar : std_logic; variable multiplicandVar : std_logic_vector(Multiplicand'length-1 downto 0); variable multiplierVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); variable resultVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); begin multiplicandVar := abs(multiplicand); multiplierVar := ext(abs(Multiplier),multiplierVar'length); negVar := multiplier(multiplier'left) xor multiplicand(multiplicand'left); resultVar := (others => '0'); for loopVar in multiplicandVar'reverse_range loop if (multiplicandVar(loopVar) = '1') then resultVar := resultVar + multiplierVar; end if; multiplierVar := multiplierVar(multiplierVar'high-1 downto 0) & '0'; end loop; if (negVar = '1') then return neg(resultVar); else return resultVar; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : mult_us -- -- DESCRIPTION : This function multiplies an unsigned std_logic vector -- value by another unsigned std_logic_vector value -- -- NOTES : This function is provided for in std_logic_arith ------------------------------------------------------------------------------ function mult_us(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector is variable multiplicandVar : std_logic_vector(Multiplicand'length-1 downto 0); variable multiplierVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); variable resultVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); begin multiplicandVar := multiplicand; multiplierVar := ext(Multiplier,multiplierVar'length); resultVar := (others => '0'); for loopVar in multiplicandVar'reverse_range loop if (multiplicandVar(loopVar) = '1') then resultVar := resultVar + multiplierVar; end if; multiplierVar := multiplierVar(multiplierVar'high-1 downto 0) & '0'; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : nat_to_slv (convert natural to std_logic_vector) -- -- DESCRIPTION : This function converts a natural value to a -- std_logic_vector with a range just large enough -- to represent it -- -- NOTES -- ------------------------------------------------------------------------------ function nat_to_slv(natVal : natural) return std_logic_vector is begin return conv_std_logic_vector(natVal,vlfn(natVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : neg -- -- DESCRIPTION : This function toggles the sign of the value passed -- -- NOTES : -- ------------------------------------------------------------------------------ function neg(VectorVal : std_logic_vector) return std_logic_vector is variable oneFndVar : boolean; variable resultVar : std_logic_vector(VectorVal'length-1 downto 0); begin oneFndVar := false; resultVar := VectorVal; resultVar := not resultVar; -- invert all bits resultVar := resultVar + '1'; -- then add one return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : now -- -- DESCRIPTION : This function returns a string representation -- of the current simulation time -- -- NOTES : -- ------------------------------------------------------------------------------ -- synopsys translate_off impure function now return string is variable lineVar : line; variable resultVar : string(1 to time'image(now)'length); begin --Std.TextIO.Write(lineVar, vectorVal); Write(lineVar, time'image(now)); resultVar(lineVar.all'range) := lineVar.all; deallocate(lineVar); return resultVar; end function; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : pipelined_comparator_latency -- -- DESCRIPTION : returns the register compare present in the -- module named : "Pipelined_Comparator" -- -- NOTES: -- -- ------------------------------------------------------------------------------ function pipelined_comparator_latency(busWidthVal : integer) return string is variable latencyVar : integer; -- subtract out the latency of the pipelined comparison variable loopEnableVar : boolean; begin latencyVar := 0; loopEnableVar := TRUE; comparator_latency_computer : while loopEnableVar loop -- compute the expected latency for a pipelined comparator if (2**(2*latencyVar+1) >= busWidthVal) then -- if the current value that latencyVar will have is enough to cover the given vector then stop here loopEnableVar := FALSE; end if; latencyVar := latencyVar + 1; -- minimum latency of 1, increment by 1 before exiting loop end loop comparator_latency_computer; return to_string(-latencyVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : pipelined_comparator_latency -- -- DESCRIPTION : returns the register compare latency needed for the -- module named : "Pipelined_Comparator" -- -- NOTES: -- -- ------------------------------------------------------------------------------ function pipelined_comparator_latency(timeStrVal : string; freqStrVal : string) return string is variable latencyVar : integer; -- subtract out the latency of the pipelined comparison variable loopEnableVar : boolean; variable stopVar : std_logic_vector(cufth(timeStrVal,freqStrVal) downto 0); begin latencyVar := 0; loopEnableVar := TRUE; stopVar := (others => '1'); stop_value_comparator_latency_computer : while loopEnableVar loop -- compute the expected latency for a pipelined stop value comparator if (2**(2*latencyVar+1) >= stopVar'length) then -- if the current value that latencyVar will have is enough to cover the given vector then stop here loopEnableVar := FALSE; end if; latencyVar := latencyVar + 1; -- minimum latency of 1, increment by 1 before exiting loop end loop stop_value_comparator_latency_computer; return to_string(-latencyVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce -- -- DESCRIPTION : This function returns a vector with the extra sign -- bits removed -- -- NOTES : -- ------------------------------------------------------------------------------ function reduce(vectorVal : std_logic_vector) return std_logic_vector is variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(vectorVal'length-1 downto 0); begin resultVar := vectorVal; lengthVar := 0; MSBFound := False; for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar; -- this is the minimum number of bits needed to represent the absolute value. MSBFound := True; end if; end loop; lengthVar := lengthVar + 1; -- And add one for the sign bit return resultVar(lengthVar downto 0); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_high -- -- DESCRIPTION : This function returns an integer value representing -- the vector'high value of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- -- ------------------------------------------------------------------------------ function reduce_high(vectorVal : std_logic_vector) return integer is variable interimVar : std_logic_vector(vectorVal'length-1 downto 0); variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(MAX_VECT_SIZE downto 0); begin interimVar := vectorVal; lengthVar := 0; MSBFound := False; resultVar := sxt(interimVar,resultVar'length); -- sign extend the value passed to the size of the slv variable for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit MSBFound := True; end if; end loop; return lengthVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_high_unsigned -- -- DESCRIPTION : This function returns an integer value representing -- the vector'high value of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- -- ------------------------------------------------------------------------------ function reduce_high_unsigned(vectorVal : std_logic_vector) return integer is variable interimVar : std_logic_vector(vectorVal'length-1 downto 0); variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(MAX_VECT_SIZE downto 0); begin interimVar := vectorVal; lengthVar := 0; MSBFound := False; resultVar := sxt(interimVar,resultVar'length); -- sign extend the value passed to the size of the slv variable for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar; -- this is the minimum number of bits needed to represent the absolute value. MSBFound := True; end if; end loop; return lengthVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_length -- -- DESCRIPTION : This function returns an integer value representing -- the length of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- ------------------------------------------------------------------------------ function reduce_length(vectorVal : std_logic_vector) return integer is begin return reduce_high(vectorVal) + 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_length_unsigned -- -- DESCRIPTION : This function returns an integer value representing -- the length of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- ------------------------------------------------------------------------------ function reduce_length_unsigned(vectorVal : std_logic_vector) return integer is begin return reduce_high_unsigned(vectorVal) + 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_unsigned -- -- DESCRIPTION : This function returns a vector with all sign -- bits removed -- -- NOTES : -- ------------------------------------------------------------------------------ function reduce_unsigned(vectorVal : std_logic_vector) return std_logic_vector is variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(vectorVal'length-1 downto 0); begin resultVar := vectorVal; lengthVar := 0; MSBFound := False; for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar; -- this is the minimum number of bits needed to represent the absolute value. MSBFound := True; end if; end loop; return resultVar(lengthVar downto 0); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : rounddown -- -- DESCRIPTION : This function rounds the first integer value down to the -- next lower multiple of the second integer passed -- -- NOTES : -- ------------------------------------------------------------------------------ function rounddown(int1Val : integer; int2Val : integer) return integer is begin return integer(floor(real(int1Val)/real(int2Val))*real(int2Val)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : roundup -- -- DESCRIPTION : This function rounds the first integer value up to the -- next higher multiple of the second integer passed -- -- NOTES : -- ------------------------------------------------------------------------------ function roundup(int1Val : integer; int2Val : integer) return integer is begin return integer(ceil(real(int1Val)/real(int2Val))*real(int2Val)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : seq (string equality function) -- -- DESCRIPTION : This function returns true if both string values passed -- are identical -- -- NOTES : This function was added because the the synthesis tool -- didn't support a boolean string equality operation test. -- Also, adding a new overloaded operator "=" caused problems -- with the simulator -- ------------------------------------------------------------------------------ function seq(str1Val : string; str2Val : string) return boolean is variable char1Var : character; variable char2Var : character; variable resultVar : boolean; variable str1Var : string(1 to str1Val'length); variable str2Var : string(1 to str2Val'length); begin resultVar := true; str1Var := str1Val; str2Var := str2Val; for loopVar in str1Var'range loop if (str1Var(loopVar) /= str2Var(loopVar)) then resultVar := false; end if; end loop; return resultVar; end function; -------------------------------------------------------------------------------- ---- ---- FUNCTION NAME : shift ---- ---- DESCRIPTION : This function returns a std_logic_vector shifted ---- by the number of integer places specified. This provides ---- an easy way to multiply or divide by 2^(natVal) ---- ---- ---- NOTES ---- -------------------------------------------------------------------------------- --function shift(vectorVal : std_logic_vector; -- intVal : integer) return std_logic_vector is -- variable resultVar : std_logic_vector(vectorVal'length-1 downto 0); --begin -- resultVar := vectorVal; -- resultVar := (others => '0'); -- resultVar(resultVar'high downto resultVar'high-vectorVal'length+1) := resultVar; -- return resultVar; --end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : shl (shift left) -- -- DESCRIPTION : This function returns a std_logic_vector shifted left -- by the number of binary places specified. This provides -- an easy way to multiply by 2^(natVal) -- -- -- NOTES -- ------------------------------------------------------------------------------ function shl(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector is variable interimVar : std_logic_vector(vectorVal'length-1 downto 0); variable resultVar : std_logic_vector(vectorVal'length+natVal-1 downto 0); begin interimVar := vectorVal; resultVar := (others => '0'); resultVar(resultVar'high downto resultVar'high-vectorVal'length+1) := interimVar; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd -- -- DESCRIPTION : This function converts an unsigned, decending range, -- std logic vector value into a -- packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number of BCD digits passed to the function. -- -- NOTES -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to -- ------------------------------------------------------------------------------ function slv_to_bcd(vectorVal : std_logic_vector; BCD_DigitsVal : integer) return std_logic_vector is type resultArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector of std_logic_vector(4*BCD_DigitsVal-1 downto 0); -- array width is determined by the number of BCD digits to output variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if the next BCD Digit is computed without carry from the current BCD value variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if the next BCD Digit is computed with carry from the current BCD value variable InnrLoopVar : integer := 0; -- inner loop index variable variable OutrLoopVar : integer := 0; -- outer loop index variable variable ResultVar : resultArrayType; -- BCD value result variable variable VectorVar : std_logic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; ResultVar(0) := (others => '0'); -- set the initial entry in the results array to zero for OutrLoopVar in VectorVar'high downto 0 loop -- start at the MSB of the std logic vector input and work down CarryVar(0) := VectorVar(OutrLoopVar); -- read in the next bit of the slv input into the lowest carry bit for InnrLoopVar in 0 to BCD_DigitsVal-1 loop -- start at the LSB of the BCD output BCD_WoCarVar := ResultVar(VectorVar'length - OutrLoopVar -1) -- read the results of the previous calculation (4*InnrLoopVar+3 downto 4*InnrLoopVar); BCD_WiCarVar := BCD_WoCarVar - "0101"; -- compute the result for the current BCD digit if a carry to the next digit will be needed if (BCD_WoCarVar > "0100") then -- if the digit is 5 or greater ("0101") then the result of the binary shift left "10100" = decimal 16, which is to great to represent in one BCD digit so then CarryVar(InnrLoopVar+1) := '1'; -- we carry a digit to the next BCD digit ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- and we use the lesser value for the current digit along with the carry value from the previous BCD digit else -- otherwise the digit is small enough to be represented in one BCD digit when a binary shift in is performed CarryVar(InnrLoopVar+1) := '0'; ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- so we write the value to the result variable along with any carry value from a previous BCD digit end if; end loop; end loop; return ResultVar(VectorVar'high+1); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd -- -- DESCRIPTION : This function converts an unsigned, decending range, -- binary value into a packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector is type resultArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector of std_logic_vector(4*dpfslvr(vectorVal)-1 downto 0); -- array width is determined by the number of BCD digits to output variable CarryVar : std_logic_vector (dpfslvr(vectorVal) downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if no carry to the next BCD Digit is needed variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if carry to the next BCD Digit is needed variable InnrLoopVar : integer := 0; -- inner loop index variable variable OutrLoopVar : integer := 0; -- outer loop index variable variable ResultVar : resultArrayType; -- BCD value result variable variable VectorVar : std_logic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; ResultVar(0) := (others => '0'); -- set the initial entry in the results array to zero for OutrLoopVar in VectorVar'high downto 0 loop -- start at the MSB of the std logic vector input and work down CarryVar(0) := VectorVar(OutrLoopVar); -- read in the next bit of the slv input into the lowest carry bit for InnrLoopVar in 0 to CarryVar'high-1 loop -- start at the LSB of the BCD output BCD_WoCarVar := ResultVar(VectorVar'length - OutrLoopVar -1) -- read the results of the previous calculation (4*InnrLoopVar+3 downto 4*InnrLoopVar); BCD_WiCarVar := BCD_WoCarVar - "0101"; -- compute the result for the current BCD digit if a carry to the next digit will be needed if (BCD_WoCarVar > "0100") then -- if the digit is 5 or greater ("0101") then the result of the binary shift left "10100" = decimal 16, which is to great to represent in one BCD digit so then CarryVar(InnrLoopVar+1) := '1'; -- we carry a digit to the next BCD digit ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- and we use the lesser value for the current digit along with the carry value from the previous BCD digit else -- otherwise the digit is small enough to be represented in one BCD digit when a binary shift in is performed CarryVar(InnrLoopVar+1) := '0'; ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- so we write the value to the result variable along with any carry value from a previous BCD digit end if; end loop; end loop; return ResultVar(VectorVar'high+1); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd_pipe -- -- DESCRIPTION : This function converts an unsigned, decending range, -- binary value into a packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it. -- it is for use in pipelined implementations where -- the binary coded decimal output is registered -- and passed back to the function along with the binary -- vector input to be shifted out of its MSB -- register and into the function as a new bit. -- -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) -- -- "width mismatch" errors here are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function slv_to_bcd_pipe( BCD_RVal : std_logic_vector; -- registered output of this function fed back in MSB_Val : std_logic; -- msb of binary value being shifted in BCD_DigitsVal : integer) return std_logic_vector is -- binary coded decimal arithmetic shift left variable BCDVar : std_logic_vector(BCD_RVal'length-1 downto 0); variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); variable BCD_WiCarVar : std_logic_vector(3 downto 0); variable ResultVar : std_logic_vector(4*BCD_DigitsVal-1 downto 0); begin BCDVar := BCD_RVal; for loopVar in 0 to BCD_DigitsVal-1 loop CarryVar(0) := MSB_Val; BCD_WoCarVar := BCDVar(4*loopVar+3 downto 4*loopVar); BCD_WiCarVar := BCD_WoCarVar - "0101"; if (BCD_WoCarVar > "0100") then CarryVar(loopVar+1) := '1'; ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WiCarVar(2 downto 0) & CarryVar(loopVar); else CarryVar(loopVar+1) := '0'; ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WoCarVar(2 downto 0) & CarryVar(loopVar); end if; end loop; return ResultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_int -- -- DESCRIPTION : This function converts a string to an integer -- -- NOTES : -- ------------------------------------------------------------------------------ function str_to_int(stringVal : string) return integer is variable decPlace : integer := 1; variable stringVar : string(1 to stringVal'length); variable negVar : boolean; -- used to indicate whether or not the string represents a negative number variable resultVar : integer; variable vectorParseVar : character; begin negVar := false; resultVar := 0; stringVar := stringVal; for loopVar in stringVar'range loop vectorParseVar := stringVar(loopVar); case vectorParseVar is when '-' => negVar := true; when '0' => resultVar := (resultVar * 10) + 0; when '1' => resultVar := (resultVar * 10) + 1; when '2' => resultVar := (resultVar * 10) + 2; when '3' => resultVar := (resultVar * 10) + 3; when '4' => resultVar := (resultVar * 10) + 4; when '5' => resultVar := (resultVar * 10) + 5; when '6' => resultVar := (resultVar * 10) + 6; when '7' => resultVar := (resultVar * 10) + 7; when '8' => resultVar := (resultVar * 10) + 8; when '9' => resultVar := (resultVar * 10) + 9; when '.' => if (negVar) then -- ignore everything after a decimal point return -resultVar; else return resultVar; end if; when others => end case; end loop; if (negVar) then -- ignore everything after a decimal point return -resultVar; else return resultVar; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_line -- -- DESCRIPTION : This function converts a string to a line -- -- NOTES : -- ------------------------------------------------------------------------------ -- synopsys translate_off function str_to_line(strVal : string) return line is variable lineVar : line; begin --Std.TextIO.Write(lineVar, vectorVal); Write(lineVar, strVal); return lineVar; end function; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_led -- -- DESCRIPTION : This function converts a Seven Segment LED -- string of any length to a std_logic_vector -- -- NOTES : if the CAVal boolean input is true the output will -- be for a Common Anode (1=off) display, otherwise it will -- be for a Common Cathode (1=on)display. -- -- _____ -- | a | -- f| |b -- |_____| -- | g | -- e| |c -- |_____| -- d -- -- "width mismatch" errors here are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function str_to_led(stringVal : string; CAVal : boolean) return std_logic_vector is variable stringVar : string(stringVal'length downto 1); variable resultVar : std_logic_vector(7*StringVal'length downto 1); variable vectorParseVar : character; begin stringVar := stringVal; for loopVar in StringVar'range loop vectorParseVar := StringVar(loopVar); case vectorParseVar is -- Illuminated -- character Segment -- shown abcdefg when ' ' => resultVar(7*loopVar downto 7*loopVar-6) := "0000000"; when '"' => resultVar(7*loopVar downto 7*loopVar-6) := "0100010"; when ''' => resultVar(7*loopVar downto 7*loopVar-6) := "0100000"; when '-' => resultVar(7*loopVar downto 7*loopVar-6) := "0000001"; when '/' => resultVar(7*loopVar downto 7*loopVar-6) := "0100101"; when '0' | 'D' => resultVar(7*loopVar downto 7*loopVar-6) := "1111110"; when '1' => resultVar(7*loopVar downto 7*loopVar-6) := "0110000"; when '2' => resultVar(7*loopVar downto 7*loopVar-6) := "1101101"; when '3' => resultVar(7*loopVar downto 7*loopVar-6) := "1111001"; when '4' => resultVar(7*loopVar downto 7*loopVar-6) := "0110011"; when '5' | 'S' => resultVar(7*loopVar downto 7*loopVar-6) := "1011011"; when '6' => resultVar(7*loopVar downto 7*loopVar-6) := "1011111"; when '7' => resultVar(7*loopVar downto 7*loopVar-6) := "1110010"; when '8' | 'B' => resultVar(7*loopVar downto 7*loopVar-6) := "1111111"; when '9' => resultVar(7*loopVar downto 7*loopVar-6) := "1110011"; when '=' => resultVar(7*loopVar downto 7*loopVar-6) := "0001001"; when '?' => resultVar(7*loopVar downto 7*loopVar-6) := "1100101"; when 'A' => resultVar(7*loopVar downto 7*loopVar-6) := "1110111"; when 'C' => resultVar(7*loopVar downto 7*loopVar-6) := "1001110"; when 'E' => resultVar(7*loopVar downto 7*loopVar-6) := "1001111"; when 'F' => resultVar(7*loopVar downto 7*loopVar-6) := "1000111"; when 'G' => resultVar(7*loopVar downto 7*loopVar-6) := "1011110"; when 'H' => resultVar(7*loopVar downto 7*loopVar-6) := "0110111"; when 'I' => resultVar(7*loopVar downto 7*loopVar-6) := "0000110"; when 'J' => resultVar(7*loopVar downto 7*loopVar-6) := "1111100"; when 'L' => resultVar(7*loopVar downto 7*loopVar-6) := "0001110"; when 'O' => resultVar(7*loopVar downto 7*loopVar-6) := "1111110"; when 'P' => resultVar(7*loopVar downto 7*loopVar-6) := "1100111"; when 'T' => resultVar(7*loopVar downto 7*loopVar-6) := "1000110"; when 'U' => resultVar(7*loopVar downto 7*loopVar-6) := "0111110"; when 'Y' => resultVar(7*loopVar downto 7*loopVar-6) := "0100111"; when 'Z' => resultVar(7*loopVar downto 7*loopVar-6) := "1101101"; when '\' => resultVar(7*loopVar downto 7*loopVar-6) := "0010011"; when ']' => resultVar(7*loopVar downto 7*loopVar-6) := "1111000"; when '^' => resultVar(7*loopVar downto 7*loopVar-6) := "1100010"; when '_' => resultVar(7*loopVar downto 7*loopVar-6) := "0001000"; when 'b' => resultVar(7*loopVar downto 7*loopVar-6) := "0011111"; when 'c' => resultVar(7*loopVar downto 7*loopVar-6) := "0001101"; when 'd' => resultVar(7*loopVar downto 7*loopVar-6) := "0111101"; when 'g' => resultVar(7*loopVar downto 7*loopVar-6) := "1111011"; when 'h' => resultVar(7*loopVar downto 7*loopVar-6) := "0010111"; when 'j' => resultVar(7*loopVar downto 7*loopVar-6) := "0111100"; when 'l' => resultVar(7*loopVar downto 7*loopVar-6) := "0111000"; when 'n' => resultVar(7*loopVar downto 7*loopVar-6) := "0010101"; when 'o' => resultVar(7*loopVar downto 7*loopVar-6) := "0011101"; when 'r' => resultVar(7*loopVar downto 7*loopVar-6) := "0000101"; when 'u' => resultVar(7*loopVar downto 7*loopVar-6) := "0011100"; when '¬' => resultVar(7*loopVar downto 7*loopVar-6) := "0010001"; when '¯' => resultVar(7*loopVar downto 7*loopVar-6) := "1000000"; when '°' => resultVar(7*loopVar downto 7*loopVar-6) := "1100011"; when others => end case; end loop; if (CAVal) then return not resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to else return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_slv -- -- DESCRIPTION : This function converts an std_logic_vector value (in string form) -- of any length to a std_logic_vector -- -- NOTES : -- -- ------------------------------------------------------------------------------ function str_to_slv(stringVal : string) return std_logic_vector is variable resultVar : std_logic_vector(MAX_VECT_SIZE downto 0) := (others => '0'); variable stringParseVar : character; variable stringVar : string(1 to stringVal'length) := stringVal; variable validBitCountVar : integer := 0; begin straight_to_slv : for loopVar in stringVar'reverse_range loop stringParseVar := stringVar(loopVar); case stringParseVar is when '0' => resultVar(validBitCountVar) := '0'; validBitCountVar := validBitCountVar + 1; when '1' => resultVar(validBitCountVar) := '1'; validBitCountVar := validBitCountVar + 1; when others => end case; end loop straight_to_slv; return resultVar(validBitCountVar-1 downto 0); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strh -- -- DESCRIPTION : This function returns the high value of a string vector -- -- -- NOTES -- -- ------------------------------------------------------------------------------ function strh(stringVal : string) return integer is begin return stringVal'high; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv -- -- DESCRIPTION : This function converts an integer value (in string form) -- of any length to a std_logic_vector -- -- NOTES : -- -- ------------------------------------------------------------------------------ function strval_to_slv(stringVal : string) return std_logic_vector is begin return strval_to_slv(stringVal,-15); -- default to 1fs time base end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv -- -- DESCRIPTION : This function has 3 modes of operations depending on what -- it is presented with. -- 1. It will convert an integer, in string form, into a -- standard logic vector. -- 2. It will convert a time or period value, in string form, -- into a standard logic vector. -- 3. It will convert a frequency value, in string form, -- into a standard logic vector of that frequency's period. -- -- NOTES : This function uses the integer value passed as the exponent -- of the timebase to use for its computations. -- It supports both positive and negative numbers -- as well as positive and negative exponents. It supports -- multiple time unit per string as long as there are no -- exponents used. No other units may start with the -- character 's' unless the "ec" detection portion -- of the "seconds" unit portion is uncommented -- and 's' is no longer used as a unit for "seconds" -- -- Time units supported -- -- 0.000 000 000 000 000 000 000 001 yoctosecond [ ys ] 10^(-24) -- 0.000 000 000 000 000 000 001 zeptosecond [ zs ] 10^(-21) -- 0.000 000 000 000 000 001 attosecond [ as ] 10^(-1 -- 0.000 000 000 000 001 femtosecond [ fs ] 10^(-15) -- 0.000 000 000 001 [ trillionth ] picosecond [ ps ] 10^(-12) -- 0.000 000 001 [ billionth ] nanosecond [ ns ] 10^(-9) -- 0.000 001 [ millionth ] microsecond [ µs ] 10^(-6) -- 0.001 [ thousandth ] millisecond [ ms ] 10^(-3) -- 0.01 [ hundredth ] centisecond [ cs ] 10^(-2) -- 1.0 second [ s or sec ] 10^(0) -- 60.0 minute [ min ] 10^(0) -- 3600.0 hour [ hr ] 10^(0) -- 86,400.0 day [ day ] 10^(0) -- -- -- Frequency units supported -- -- 1 hertz [ hz ] 10^(0) -- 1,000 kilohertz [ khz ] 10^(3) -- 1,000,000 megahertz [ mhz ] 10^(6) -- 1,000,000,000 gigahertz [ ghz ] 10^(9) -- 1,000,000,000,000 terahertz [ thz ] 10^(12) -- 1,000,000,000,000,000 petahertz [ phz ] 10^(15) -- 1,000,000,000,000,000,000 exahertz [ ehz ] 10^(1 -- 1,000,000,000,000,000,000,000 zetahertz [ zhz ] 10^(21) -- 1,000,000,000,000,000,000,000,000 yottahertz [ yhz ] 10^(24) -- -- EXAMPLE "1 day, 3 hrs, 15.298 seconds" -- "66,000,000 Hz" "66,000,000.000 Hz" "66 MHz" "66E6 Hz" "66E+6 Hz" "66.000E+6 Hz" -- "66,000,000 us" "66,000,000.000 us" "66 us" "66E6 us" "66E+6 us" "66.000E+6 us" -- -- ------------------------------------------------------------------------------ function strval_to_slv(stringVal : string; intVal : integer) return std_logic_vector is constant \10\ : std_logic_vector(3 downto 0) := "1010"; -- 10 constant \60\ : std_logic_vector(5 downto 0) := "111100"; -- 60 constant \3600\ : std_logic_vector(11 downto 0) := "111000010000"; -- 3600 constant \86400\ : std_logic_vector(16 downto 0) := "10101000110000000"; -- 86,400 (solar day) variable baseVar : integer; -- exponent of the timebase i.e. 1fs = 1E-15 seconds so the timebase = 15 variable decPlacesVar : integer; -- used to count how many numbers are after the decimal point variable decPntFndVar : boolean; -- used to flag whether or not a decimal point was found in the string variable expFndVar : boolean; -- used to flag that the exponent has been reached so that the rest of the string value will not be interpreted as part of the base value variable expVar : integer; -- used to indicated the exponent value variable freqUnitFndVar : boolean; -- used to flag whether or not the string represents a frequency variable negVar : boolean; -- used to flag whether or not the string represents a negative number variable resultVar : std_logic_vector(MAX_VECT_SIZE+16 downto 0); variable result2Var : std_logic_vector(MAX_VECT_SIZE+16 downto 0); -- used to store a result from a secondary value such as would be encounter when a value such as "1 hr 10 mins" is passed to the function variable scndTimeFndVar : boolean; -- used to indicate a second time value was found variable stringParseVar : character; -- character currently under test variable stringVar : string(1 to stringVal'length+4); -- slightly larger because string is addessed beyond the current loop to test for units variable timeBaseVar : std_logic_vector(MAX_VECT_SIZE+16 downto 0); variable timeUnitFndVar : boolean; -- used to flag that a time unit was found (days, hrs, mins, secs) variable validBitCountVar : integer := 0; begin baseVar := -intVal; decPntFndVar := false; -- initialize to decimal point not found yet decPlacesVar := 0; expFndVar := false; -- initialize to exponent point not found yet expVar := 0; freqUnitFndVar := false; -- initialize to frequency units not found yet negVar := false; -- initialize to negative sign not found yet resultVar := (others => '0'); result2Var := (others => '0'); scndTimeFndVar := false; -- initialize to secont time value not found yet stringVar := stringVal & " "; -- tack on few extra spaces for padding so that it is possible to address beyond the current loop variable timeUnitFndVar := false; timeBaseVar := ext("01",timeBaseVar'length); for loopVar in 1 to baseVar loop timeBaseVar := mult_us(timeBaseVar(MAX_VECT_SIZE+12 downto 0), \10\); -- this value will contain the time base (in binary) when this loop completes (10^30 for a baseVar of 30) end loop; for loopVar in stringVar'range loop -- this loop parses the string value passed to this function from left to right stringParseVar := stringVar(loopVar); if (scndTimeFndVar) then resultVar := resultVar; -- if a second value has been found then just wait here for the loop to complete else case stringParseVar is when '-' => if (not decPntFndvar and not expFndVar and not freqUnitFndVar and not timeUnitFndVar) then -- expect the sign to be near the front of the string negVar := true; end if; when '0' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then -- if the decimal point was found and we're not reading an exponent then decPlacesVar := decPlacesVar + 1; -- consider this to be a number after the decimal point end if; if (not expFndVar) then -- if we are not reading the exponent then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 0; -- factor in the next digit end if; end if; when '1' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 1; end if; end if; when '2' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 2; end if; end if; when '3' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 3; end if; end if; when '4' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 4; end if; end if; when '5' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 5; end if; end if; when '6' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 6; end if; end if; when '7' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 7; end if; end if; when '8' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 8; end if; end if; when '9' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 9; end if; end if; when 'e' | 'E' => -- exponent if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- exahertz unit found for loopVar in 1 to 18 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not expFndVar and not freqUnitFndVar and not timeUnitFndVar) -- if we haven't already found an exponent, frequency unit, or time unit then expFndVar := true; -- mark that we've found it expVar := str_to_int(stringVar(loopVar to stringVal'length)); -- and capture its value end if; when '.' => decPntFndVar := true; -- mark the position of the decimal point when 'y' | 'Y' => -- yoctosecond 10^-24 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- yoctosecond unit found for loopVar in 1 to baseVar-24 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- yottahertz unit found for loopVar in 1 to 24 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'z' | 'Z' => -- zeptosecond 10^-21 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- zeptosecond unit found for loopVar in 1 to baseVar-21 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- zettahertz unit found for loopVar in 1 to 21 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'a' | 'A' => -- attosecond 10^-18 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- attosecond unit found for loopVar in 1 to baseVar-18 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'f' | 'F' => -- femtosecond 10^-15 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- femtosecond unit found for loopVar in 1 to baseVar-15 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'p' | 'P' => -- picosecond 10^-12 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- picosecond unit found for loopVar in 1 to baseVar-12 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- petahertz unit found for loopVar in 1 to 15 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'n' | 'N' => -- nanosecond 10^-9 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- nanosecond unit found for loopVar in 1 to baseVar-9 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'u' | 'U' => -- microsecond 10^-6 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- microsecond unit found for loopVar in 1 to baseVar-6 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'm' | 'M' => -- millisecond 10^-3 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- millisecond unit found for loopVar in 1 to baseVar-3 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "in")) or (seq(stringVar(loopVar+1 to loopVar+2), "iN")) or (seq(stringVar(loopVar+1 to loopVar+2), "In")) or (seq(stringVar(loopVar+1 to loopVar+2), "IN")))) then timeUnitFndVar := true; -- minute unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; resultVar := mult_us(resultVar(MAX_VECT_SIZE+10 downto 0), \60\); elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- megahertz unit found for loopVar in 1 to 6 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 's' | 'S' => if (not freqUnitFndVar and not timeUnitFndVar) -- and --((seq(stringVar(loopVar+1 to loopVar+2), "ec")) or -- (seq(stringVar(loopVar+1 to loopVar+2), "eC")) or -- (seq(stringVar(loopVar+1 to loopVar+2), "Ec")) or -- (seq(stringVar(loopVar+1 to loopVar+2), "EC")))) then timeUnitFndVar := true; -- second unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'h' | 'H' => if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 'r') or (stringVar(loopVar+1) = 'R'))) then timeUnitFndVar := true; -- hour unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; resultVar := mult_us(resultVar(MAX_VECT_SIZE+4 downto 0), \3600\); elsif (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 'z') or (stringVar(loopVar+1) = 'Z'))) then freqUnitFndVar := true; end if; when 'd' | 'D' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "ay")) or (seq(stringVar(loopVar+1 to loopVar+2), "aY")) or (seq(stringVar(loopVar+1 to loopVar+2), "Ay")) or (seq(stringVar(loopVar+1 to loopVar+2), "AY")))) then timeUnitFndVar := true; -- day unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; resultVar := mult_us(resultVar(MAX_VECT_SIZE-1 downto 0), \86400\); end if; when 'g' | 'G' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- gigahertz unit found for loopVar in 1 to 9 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'k' | 'K' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- kilohertz unit found for loopVar in 1 to 3 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 't' | 'T' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- terahertz unit found for loopVar in 1 to 12 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when others => end case; end if; end loop; if (expVar >= 0) then -- if it's a positive exponent then perform a multiplication loop for loopVar in 1 to expVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; else -- if it's a negative exponent then perform a division loop for loopVar in 1 to (-expVar) loop resultVar := resultVar / \10\; end loop; end if; if (decPntFndVar) then -- if a decimal point was present in the value then for loopVar in 1 to decPlacesVar loop -- scale the output accordingly resultVar := resultVar / \10\; end loop; end if; resultVar := resultVar + result2Var; -- add on any secondary value if (freqUnitFndVar) then -- the the string is a frequency value then resultVar := timeBaseVar / resultVar; -- invert it to convert it to a period value before returning end if; if (negVar and not timeUnitFndVar) then -- the the string is a negative value and its not a time value then resultVar := neg(resultVar); -- negate the result end if; return reduce(resultVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv_high -- -- DESCRIPTION : This function converts an integer value string -- of any length to a std_logic_vector -- -- NOTES -- -- ------------------------------------------------------------------------------ function strval_to_slv_high(stringVal : string) return integer is begin return reduce_high(strval_to_slv(stringVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv_var_base_high -- -- DESCRIPTION : This function converts an integer value string -- of any length to a std_logic_vector -- -- NOTES -- -- ------------------------------------------------------------------------------ function strval_to_slv_var_base_high(stringVal : string; intVal : integer) return integer is begin return reduce_high(strval_to_slv(stringVal,intVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : sxt2 (sign extend) -- -- DESCRIPTION : This function returns a standard logic vector, -- padded with zeros, to the length specified by intVal -- -- NOTES : -- ------------------------------------------------------------------------------ function sxt2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector is variable zeroVar : std_logic_vector(natVal - vectorVal'length - 1 downto 0) := (others => '0'); variable oneVar : std_logic_vector(natVal - vectorVal'length - 1 downto 0) := (others => '1'); variable vectorVar : std_logic_vector(vectorVal'length - 1 downto 0); begin vectorVar := vectorVal; if (vectorVar(vectorVar'high) = '1') then if (vectorVar'length >= natVal) then return vectorVar; else return oneVar & vectorVar; end if; else if (vectorVar'length >= natVal) then return vectorVar; else return zeroVar & vectorVar; end if; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_int -- -- DESCRIPTION : conv_integer function repackaged -- -- NOTES -- ------------------------------------------------------------------------------ function to_int(vectorVal : std_logic_vector) return integer is begin return conv_integer(vectorVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_period -- -- DESCRIPTION : This function returns a one cycle period value for -- a given frequency -- -- NOTES timeVar must be larger than the simulator resolution -- and is limited by the integer that can be created from -- time'pos of it's value -- -- the funtion does not work with Synplify 7.7 ------------------------------------------------------------------------------ --function to_period(freqVal : frequency) return time is -- variable resultVar : time; --begin -- resultVar := 1E9/frequency'pos(freqVal) * 1 ns; -- max of 2147.483647 ns for Precision Synthesis -- return resultVar; --end function; -- new Physical types not supported by XST -- synopsys synthesis_off function to_period(freqVal : frequency) return time is variable resultVar : time; variable timeVar : time := 1 ms; variable divVar : real := real(1 sec/timeVar); begin if (frequency'pos(freqVal) > 2_147_483_647) then assert FALSE report "Frequency value passed to function is greater than 2,147,483,647 when converted to base units." severity warning; end if; resultVar := divVar/real(frequency'pos(freqVal)) * timeVar; -- see "NOTES" return resultVar; end function; -- synopsys synthesis_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_period -- -- DESCRIPTION : This function returns a one cycle period value for -- a given frequency -- -- NOTES timeVar must be larger than the simulator resolution -- and is limited by the integer that can be created from -- time'pos of it's value -- -- the funtion does not work with Synplify 7.7 ------------------------------------------------------------------------------ --function to_period(freqVal : string) return time is -- variable resultVar : time; --begin -- resultVar := 1E9/frequency'pos(freqVal) * 1 ns; -- max of 2147.483647 ns for Precision Synthesis -- return resultVar; --end function; --function to_period(freqVal : string) return time is -- constant timeVar : time := 1 ms; -- variable divVar : real := real(1 sec/timeVar); -- variable freqVar : frequency; -- variable resultVar : time; --begin -- freqVar := cft(freqVal); -- if (frequency'pos(freqVal) > 2_147_483_647) then -- assert FALSE -- report "Frequency value passed to function is greater than 2,147,483,647 when converted to base units." -- severity warning; -- end if; -- resultVar := divVar/real(frequency'pos(freqVal)) * timeVar; -- see "NOTES" -- return resultVar; --end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (boolean) -- -- DESCRIPTION : This function returns a string value representing the -- boolean value passed to it. -- NOTES -- ------------------------------------------------------------------------------ function to_string(boolVal : boolean) return string is begin if (boolVal) then return "TRUE"; else return "FALSE"; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (integer) -- -- DESCRIPTION : This function returns a string value representing the -- integer value passed to it. -- NOTES -- ------------------------------------------------------------------------------ ------ synopsys translate_off --function to_string(intVal : integer) return string is -- variable lineVar : line; -- variable resultVar : string(1 to cfi(intVal)); --begin -- --Std.TextIO.Write(lineVar, intVal); -- Write(lineVar, integer'Image(intVal)); -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ------ synopsys translate_on function to_string(intVal : integer) return string is begin return integer'Image(intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (real) -- -- DESCRIPTION : This function returns a string value representing the -- integer value passed to it. -- NOTES -- ------------------------------------------------------------------------------ ---- synopsys translate_off --function to_string(realVal : real) return string is -- variable lengthVar : natural; -- variable lineVar : line; -- variable resultVar : string(1 to real'Image(realVal)'length); --begin -- --Std.TextIO.Write(lineVar, intVal); -- Write(lineVar, real'Image(realVal)); -- lengthVar := lineVar.all'length; -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ---- synopsys translate_on function to_string(realVal : real) return string is begin return real'Image(realVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (time) -- -- DESCRIPTION : This function returns a string value representing the -- time value passed to it. -- -- NOTES : -- ------------------------------------------------------------------------------ ---- synopsys translate_off --function to_string(timeVal : time) return string is -- variable lineVar : line; -- variable resultVar : string(1 to time'image(timeVal)'length); --begin -- --Std.TextIO.Write(lineVar, vectorVal); -- Write(lineVar, time'image(timeVal)); -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ---- synopsys translate_on function to_string(timeVal : time) return string is begin return time'image(timeVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (vector) -- -- DESCRIPTION : This function returns a string value representing the -- vector value passed to it. -- NOTES -- -- 'U', -- Uninitialized -- 'X', -- Forcing Unknown -- '0', -- Forcing 0 -- '1', -- Forcing 1 -- 'Z', -- High Impedance -- 'W', -- Weak Unknown -- 'L', -- Weak 0 -- 'H', -- Weak 1 -- '-' -- Don't care ------------------------------------------------------------------------------ -- synthesis tool un-friendly version ---- synopsys translate_off --function to_string(vectorVal : std_logic_vector) return string is -- variable lineVar : line; -- variable resultVar : string(1 to vectorVal'length); --begin -- --Std.TextIO.Write(lineVar, vectorVal); -- Write(lineVar, vectorVal); -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ---- synopsys translate_on -- synthesis tool friendly version function to_string(vectorVal : std_logic_vector) return string is variable lineVar : line; variable resultVar : string(1 to vectorVal'length); variable vectorVar : std_logic_vector(1 to vectorVal'length); begin vectorVar := vectorVal; for loopVar in vectorVar'range loop if (vectorVar(loopVar) = 'U') then -- 'U', -- Uninitialized resultVar(loopVar) := 'U'; elsif (vectorVar(loopVar) = 'X') then -- 'X', -- Forcing Unknown resultVar(loopVar) := 'X'; elsif (vectorVar(loopVar) = '0') then -- '0', -- Forcing 0 resultVar(loopVar) := '0'; elsif (vectorVar(loopVar) = '1') then -- '1', -- Forcing 1 resultVar(loopVar) := '1'; elsif (vectorVar(loopVar) = 'Z') then -- 'Z', -- High Impedance resultVar(loopVar) := 'Z'; elsif (vectorVar(loopVar) = 'W') then -- 'W', -- Weak Unknown resultVar(loopVar) := 'W'; elsif (vectorVar(loopVar) = 'L') then -- 'L', -- Weak 0 resultVar(loopVar) := 'L'; elsif (vectorVar(loopVar) = 'H') then -- 'H', -- Weak 1 resultVar(loopVar) := 'H'; elsif (vectorVar(loopVar) = '-') then -- '-' -- Don't care resultVar(loopVar) := '-'; end if; end loop; return resultVar; end function; -------------------------------------------------------------------------------- ---- ---- PROCEDURE NAME : transpose ---- ---- DESCRIPTION : This procedure returns the transpose of an array ---- ---- NOTES : column 1 -> row 1 ---- column 2 -> row 2 ---- -------------------------------------------------------------------------------- --procedure( transpose(arrayVal : array_type) return array_type is -- variable resultVar : std_ulogic_vector(vectorVal'range); --begin -- for loopVar in vectorVal'low to vectorVal'high loop -- resultVar(resultVar'high-loopVar) := vectorVal(loopVar); -- end loop; -- return resultVar; --end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vhfi (vector high for integer) -- -- DESCRIPTION : This function returns the 'high value to be used -- in the range declaration of a vector used to -- represent the integer value passed to it. -- -- WARNING: This function assumes the rest of the -- range declaration of the vector -- will be "downto 0" -- -- NOTES : see vlfi for more information -- -- EXAMPLE : ------------------------------------------------------------------------------ function vhfi(intVal : integer) return natural is begin return vlfi(intVal) - 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vhfn (vector high for natural) -- -- DESCRIPTION : This function returns the 'high value to be used -- in the range declaration of a vector used to -- represent the natural value passed to it. -- -- WARNING: This function assumes the rest of the -- range declaration of the vector -- will be "downto 0" -- -- NOTES : see vlfn for more information -- -- EXAMPLE : ------------------------------------------------------------------------------ function vhfn(natVal : natural) return natural is begin return vlfn(natVal) - 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vlfi (vector length for integer) -- -- DESCRIPTION : This function returns an integer representing the -- length of the vector required to represent -- the integer value passed to it. This includes -- the sign bit; hence the "resultVar := loopVar + 1;" -- -- NOTES : type integer is range -2147483648 to 2147483647; -- This function can be used in code intended for synthesis -- Using a 31 bit variable strips off the sign bit that -- the conversion function generates. This allows us -- to place the sign bit in the new location at the top -- of the vector. -- -- EXAMPLE : -2147483648 passed, convertion to logic vector gives -- 0000000000000000000000000000000. Bit 31 is '0' and -- a sign bit is needed so 31 + 1 = 32 bits are needed to -- represent this value -- -- given intVal = 32 -- slvVar is assigned 0000000000000000000000000100000 -- "if" condition becomes true for loopVar = 6 -- result is 7 (6 bits to represent 32, plus the sign bit) ------------------------------------------------------------------------------ function vlfi(intVal : integer) return natural is variable resultVar : natural; variable slvVar : std_logic_vector(31 downto 1); -- range of 31 downto 1 used because the numbering is correct for the positional location of the bits begin slvVar := conv_std_logic_vector(intVal,slvVar'length); -- convert the integer passed to the function to a 31 bit logic vector if (intVal > 0) then -- if the integer is positive then for loopVar in slvVar'range loop -- start at the top of the vector and index down if (slvVar(loopVar) = '1') then -- and if a bit is asserted then return loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit end if; end loop; elsif (intVal = 0) then -- '0' has no value and, therefore, needs no sign bit return 1; elsif (intVal = -1) then -- '-1' is a special case which contains no zeros so the following algorithm would fail. return 2; elsif (intVal < -1) then -- if the integer is negative then for loopVar in slvVar'range loop -- start at the top of the vector and index down if (slvVar(loopVar) = '0') then -- and if a bit is asserted then return loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit end if; end loop; end if; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vlfn (vector length for natural) -- -- DESCRIPTION : This function returns an integer representing the -- length of the vector required to represent -- the natural value passed to it. There is no -- sign bit needed so "resultVar := loopVar;" -- -- NOTES : subtype natural is integer range 0 to 2_147_483_647; -- This function can be used in code intended for synthesis -- -- EXAMPLE : given natVal = 32 -- slvVar is assigned 0000000000000000000000000100000 -- "if" condition becomes true for loopVar = 6 -- result is 6 (6 bits to represent 32, no sign bit needed) ------------------------------------------------------------------------------ function vlfn(natVal : natural) return natural is variable resultVar : natural; variable slvVar : std_logic_vector(31 downto 1); begin slvVar := conv_std_logic_vector(natVal,slvVar'length); if (natVal > 2_147_483_647) then assert false report "value exceeds 2,147,483,647" severity warning; return 0; elsif (natVal > 0) then for loopVar in slvVar'range loop if (slvVar(loopVar) = '1') then return loopVar; end if; end loop; else return 1; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vrfi (vector range for integer) -- -- DESCRIPTION : This function returns a std_logic_vector of the same range -- required to represent the integer value passed to it. -- This includes the sign bit; -- -- NOTES : subtype natural is integer range 0 to 2_147_483_647; -- This function can be used in code intended for synthesis -- ------------------------------------------------------------------------------ function vrfi(intVal : integer) return std_logic_vector is variable slvVar : std_logic_vector(vhfi(intVal) downto 0); attribute slv_high : natural; attribute slv_low : natural; attribute slv_range : natural; attribute slv_high of slvVar : variable is slvVar'high; attribute slv_low of slvVar : variable is slvVar'low; --attribute slv_range of slvVar : variable is slvVar'range; begin return slvVar; end function; -------------------------------------------------------------------------------- ---- ---- FUNCTION NAME : vrfi (vector range for integer) ---- ---- DESCRIPTION : This function returns a std_logic_vector of the same range ---- required to represent the integer value passed to it. ---- This includes the sign bit; ---- hence the "resultVar := loopVar + 1;" ---- ---- NOTES : subtype natural is integer range 0 to 2_147_483_647; ---- This function cannot be used in code intended for synthesis ---- -------------------------------------------------------------------------------- ---- synopsys translate_off --function vrfi(intVal : integer) return std_logic_vector is -- type slv_ptr is access std_logic_vector; -- variable size : slv_ptr; -- variable resultVar : natural; -- variable slvVar : std_logic_vector(31 downto 1); --begin -- slvVar := conv_std_logic_vector(intVal,slvVar'length); -- convert the integer passed to the function to a 31 bit logic vector -- if (intVal > 0) then -- if the integer is positive then -- for loopVar in slvVar'range loop -- start at the top of the vector and index down -- if (slvVar(loopVar) = '1') then -- and if a bit is asserted then -- resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit -- exit; -- end if; -- end loop; -- elsif (intVal = 0) then -- '0' has no value and, therefore, needs no sign bit -- resultVar := 1; -- elsif (intVal = -1) then -- '-1' is a special case which contains no zeros so the following algorithm would fail. -- resultVar := 2; -- elsif (intVal < -1) then -- if the integer is negative then -- for loopVar in slvVar'range loop -- start at the top of the vector and index down -- if (slvVar(loopVar) = '0') then -- and if a bit is asserted then -- resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit -- exit; -- end if; -- end loop; -- end if; -- size := new std_logic_vector(resultVar-1 downto 0); ---- return size.all'range; -- return size.all; -- deallocate(size); --end function; ---- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vrfn (vector range for natural) -- -- DESCRIPTION : This function returns an std_logic_vector representing the -- length of the vector required to represent -- the natural value passed to it. -- -- NOTES : subtype natural is integer range 0 to 2_147_483_647; -- This function can be used in code intended for synthesis -- ------------------------------------------------------------------------------ function vrfn(natVal : natural) return std_logic_vector is variable slvVar : std_logic_vector(vhfn(natVal) downto 0); attribute slv_high : natural; attribute slv_low : natural; attribute slv_range : natural; attribute slv_high of slvVar : variable is slvVar'high; attribute slv_low of slvVar : variable is slvVar'low; --attribute slv_range of slvVar : variable is slvVar'range; begin return slvVar; end function; -------------------------------------------------------------------------------- ---- ---- FUNCTION NAME : vrfn (vector range for natural) ---- ---- DESCRIPTION : This function returns an std_logic_vector representing the ---- length of the vector required to represent ---- the natural value passed to it. ---- ---- NOTES : subtype natural is integer range 0 to 2_147_483_647; ---- This function cannot be used in code intended for synthesis ---- -------------------------------------------------------------------------------- ---- synopsys translate_off --function vrfn(natVal : natural) return std_logic_vector is -- type slv_ptr is access std_logic_vector; -- variable size : slv_ptr; -- variable resultVar : natural; -- variable slvVar : std_logic_vector(31 downto 1); --begin -- slvVar := conv_std_logic_vector(natVal,slvVar'length); -- if (natVal > 0) then -- for loopVar in slvVar'range loop -- if (slvVar(loopVar) = '1') then -- resultVar := loopVar; -- exit; -- end if; -- end loop; -- else -- resultVar := 1; -- end if; -- size := new std_logic_vector(resultVar-1 downto 0); -- return size.all; -- deallocate(size); --end function; ---- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : xnor_reduce (multiple input xnor gate) -- -- DESCRIPTION : -- -- NOTES : -- ------------------------------------------------------------------------------ function xnor_reduce (vectorVal : std_logic_vector) return std_logic is begin return not(xor_reduce(vectorVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : xor_reduce (multiple input xor gate) -- -- DESCRIPTION : -- -- NOTES : -- ------------------------------------------------------------------------------ function xor_reduce (vectorVal : std_logic_vector) return std_logic is variable MSB, LSB : std_logic; variable halfway : integer; variable vectorVar : std_logic_vector(vectorVal'length-1 downto 0); variable result : std_logic := '0'; begin vectorVar := vectorVal; if (vectorVar'length >= 1) then if (vectorVar'length = 1) then result := vectorVar(vectorVar'high); elsif (vectorVar'length = 2) then result := "xor"(vectorVar(vectorVar'high),vectorVar(vectorVa r'low)); else halfway := (vectorVar'length + 1) / 2; -- determine the halfway point MSB := xor_reduce(vectorVar(vectorVar'high downto halfway)); -- call the function recursively LSB := xor_reduce(vectorVar(halfway - 1 downto vectorVar'low)); -- call the function recursively result := "xor"(MSB, LSB); end if; end if; return result; end function; ------------------------------------------------------------------------------ -- -- Procedures -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a 50% duty cycle clock with the specified -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( constant clkFreqSig : in frequency; signal clkSig : out std_logic) is variable posPeriodVar : time := (to_period(clkFreqSig) * 50.0) / 100; variable negPeriodVar : time := to_period(clkFreqSig) - posPeriodVar; begin while true loop clkSig <= '1'; wait for posPeriodVar; clkSig <= '0'; wait for negPeriodVar; end loop; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a 50% duty cycle clock with the specified -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; signal clkSig : out std_logic) is variable posPeriodVar : time := (to_period(clkFreqSig) * 50.0) / 100; variable negPeriodVar : time := to_period(clkFreqSig) - posPeriodVar; begin while clkEnSig loop clkSig <= '1'; wait for posPeriodVar; clkSig <= '0'; wait for negPeriodVar; end loop; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a clock -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( signal clkEnSig : in boolean; signal clkPeriodSig : in time; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic) is variable posPeriodVar : time; variable negPeriodVar : time; begin posPeriodVar := (clkPeriodSig * clkDutySig) / 100; negPeriodVar := clkPeriodSig - posPeriodVar; if (clkResetSig) then clkSig <= '1'; elsif (clkEnSig) then if (clkSig = '1') then clkSig <= '0' after posPeriodVar; else clkSig <= '1' after negPeriodVar; end if; end if; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a clock -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic) is variable posPeriodVar : time; variable negPeriodVar : time; begin posPeriodVar := (to_period(clkFreqSig) * clkDutySig) / 100; negPeriodVar := to_period(clkFreqSig) - posPeriodVar; if (clkResetSig) then clkSig <= '1'; elsif (clkEnSig) then if (clkSig = '1') then clkSig <= '0' after posPeriodVar; else clkSig <= '1' after negPeriodVar; end if; end if; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : FF -- -- DESCRIPTION : simple flip flop procedure -- -- NOTES : synthesizeable -- ------------------------------------------------------------------------------ procedure FF ( signal Clk : in std_logic; signal Rst : in std_logic; signal D : in std_logic_vector; signal Q : out std_logic_vector) is variable zeros : std_logic_vector(Q'range) := (others => '0'); begin if (Rst = '1') then Q <= zeros; elsif Rising_Edge(Clk) then Q <= D; end if; end procedure; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd -- -- DESCRIPTION : This function converts an unsigned, decending range, -- binary value into a packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it. -- it is for use in pipelined implementations where -- the binary coded decimal output is registered -- and passed back to the function along with the binary -- vector input to be shifted out of its MSB -- register and into the function as a new bit. -- -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) ------------------------------------------------------------------------------ procedure slv_to_bcd( signal BCD_RIn : in std_logic_vector; signal BinIn : in std_logic_vector; signal BinFBIn : in std_logic_vector; signal ClkIn : in std_logic; constant BCD_DigitsVal : in integer; signal EnIn : in std_logic; signal RstLowIn : in std_logic; signal BCD_ROut : out std_logic_vector; signal Bin_ROut : out std_logic_vector; -- registed, shifted version of BinIn signal DoneOut : out std_logic) is constant BCD_ZEROS : std_logic_vector(BCD_ROut'range) := (others => '0'); constant BIN_ZEROS : std_logic_vector(BinIn'range) := (others => '0'); variable BCD_Var : std_logic_vector(BCD_ROut'range); variable BCD_RVar : std_logic_vector(BCD_ROut'range); begin if (RstLowIn = '0' or EnIn = '0') then BCD_ROut <= BCD_ZEROS; BCD_RVar := BIN_ZEROS; Bin_ROut <= BinIn; DoneOut <= '0'; elsif rising_edge(ClkIn) then Bin_ROut <= BinFBIn(BinFBIn'high-1 downto BinFBIn'low) & '0'; if (BinFBIn = BIN_ZEROS) then BCD_ROut <= BCD_RIn; DoneOut <= '1'; else BCD_ROut <= slv_to_bcd_pipe(BCD_RIn,BinFBIn(BinFBIn'high),BCD_ DigitsVal); DoneOut <= '0'; end if; end if; end procedure; ------------------------------------------------------------------------------ end extension_pack; ------------------------------------------------------------------------------ -- end of extension pack -- test bench starts below -- synopsys translate_off ------------------------------------------------------------------------------ -- Extension Pack test bench ------------------------------------------------------------------------------ library ieee, extension_lib; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use extension_lib.extension_pack.all; --use extension_lib.extension_pack_constants.all; use ieee.std_logic_textio.all; use std.textio.all; entity extension_pack_tb is end extension_pack_tb; ------------------------------------------------------------------------------ architecture behavioral of extension_pack_tb is ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- Signal declarations ------------------------------------------------------------------------------ begin star_operator_test1 : process variable slvVar : std_logic_vector(2 downto 0) := "111"; begin assert (eq(7*slvVar,"0110001")) -- 7*7 = 49 report "*1 error # 1 " & LF & to_string("0110001") & " : expected" & LF & to_string(7*slvVar) & " : actual" severity error; wait; end process; star_operator_test2 : process variable slvVar : std_logic_vector(2 downto 0) := "111"; begin assert (eq(slvVar*7,"0110001")) -- 7*7 = 49 report "*2 error # 1 " & LF & to_string("0110001") & " : expected" & LF & to_string(slvVar*7) & " : actual" severity error; wait; end process; --function "/"(DividendVal : std_logic_vector; -- DivisorVal : std_logic_vector) return std_logic_vector; slash1_operator_test : process constant slvVar : std_logic_vector(6 downto 0) := "0110001"; constant \7\ : std_logic_vector(6 downto 0) := "0000111"; begin assert (eq("0110001"/"111",\7\)) -- 49/7 = 7 report "slash1_operator_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string("0110001"/"111") & " : actual" severity error; wait; end process; --function "/"(DividendVal : std_logic_vector; -- DivisorVal : integer) return std_logic_vector; slash2_operator_test : process constant slvVar : std_logic_vector(6 downto 0) := "0110001"; begin assert (eq(slvVar/7,"0000111")) -- 49/7 = 7 report "slash2_operator_test error # 2 " & LF & to_string("0000111") & " : expected" & LF & to_string(slvVar/7) & " : actual" severity error; wait; end process; --function "/"(DividendVal : string; -- DivisorVal : integer) return std_logic_vector; slash3_operator_test : process constant var : string := "49"; begin assert (eq(var/7,"0000111")) -- 49/7 = 7 report "slash3_operator_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string(var/7) & " : actual" severity error; wait; end process; --function bcd_to_led(slvVal : std_logic_vector ; -- CAVal : boolean) return std_logic_vector; -- binary coded decimal to seven segment LED conversion bcd_to_led1_test : process constant slv1Var : std_logic_vector := x"0123456789ABCDEF"; variable slv2Var : std_logic_vector(27 downto 0); begin assert (bcd_to_led(slv1Var,true) = "0000001100111100100100000110100110001001000100000 00011010000000000110011101110011111100111001111011 0011111000111") -- 123456789ABCDEF = report "bcd_to_led_test error # 1 " & LF & to_string("000000110011110010010000011010011000100 10001000000001101000000000011001110111001111110011 10011110110011111000111") & " : expected" & LF & to_string(bcd_to_led(slv1Var,true)) & " : actual" severity error; assert (bcd_to_led(slv1Var,false) = "1111110011000011011011111001011001110110111011111 11100101111111111001100010001100000011000110000100 1100000111000") -- 123456789ABCDEF = report "bcd_to_led_test error # 2 " & LF & to_string("111111001100001101101111100101100111011 01110111111110010111111111100110001000110000001100 01100001001100000111000") & " : expected" & LF & to_string(bcd_to_led(slv1Var,false)) & " : actual" severity error; slv2Var := bcd_to_led(x"3210",False); -- 3210 assert (slv2Var = "1111001110110101100001111110") report "bcd_to_led_test error # 1 " severity error; slv2Var := bcd_to_led(x"7654",False); -- 7654 assert (slv2Var = "1110010101111110110110110011") report "bcd_to_led_test error # 2 " severity error; slv2Var := bcd_to_led(x"1098",False); -- 1098 assert (slv2Var = "0110000111111011100111111111") report "bcd_to_led_test error # 3 " severity error; slv2Var := bcd_to_led(x"3210",True); -- 3210 assert (slv2Var = "0000110001001010011110000001") report "bcd_to_led_test error # 4 " severity error; slv2Var := bcd_to_led(x"7654",True); -- 7654 assert (slv2Var = "0001101010000001001001001100") report "bcd_to_led_test error # 5 " severity error; slv2Var := bcd_to_led(x"1098",True); -- 1098 assert (slv2Var = "1001111000000100011000000000") report "bcd_to_led_test error # 6 " severity error; wait; end process; --function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed bcd_to_slv_test : process constant slvVar : std_logic_vector := x"0123456789ABCDEF"; begin assert (bcd_to_slv(slvVar) = "011100000100100010000110000111101101001110111111" ) -- 123456789ABCDEF = 123456790123455 report "bcd_to_slv_test error # 1 " & LF & to_string("011100000100100010000110000111101101001 110111111") & " : expected" & LF & to_string(bcd_to_slv(slvVar)) & " : actual" severity error; assert (bcd_to_slv(x"1234567890") = "01001001100101100000001011010010") -- 1234567890 = report "bcd_to_slv_test error # 2 " & LF & to_string("01001001100101100000001011010010") & " : expected" & LF & to_string(bcd_to_slv(slvVar)) & " : actual" severity error; assert (bcd_to_slv(x"ABCDEF") = "100010010010001111111") -- ABCDEF (1123455) report "bcd_to_slv_test error # 3 " & LF & to_string("100010010010001111111") & " : expected" & LF & to_string(bcd_to_slv(x"ABCDEF")) & " : actual" severity error; wait; end process; --function bcd_to_slv_pipe(BCD_RVal : std_logic_vector; -- BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value --function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector; -- repackaging of "To_StdLogicVector" function bv_to_slv_test : process constant bvVar : bit_vector := x"0123456789ABCDEF"; begin assert (bv_to_slv(bvVar) = x"0123456789ABCDEF") -- 123456789ABCDEF = 123456790123455 report "bv_to_slv_test error # 1 " & LF & to_string(x"0123456789ABCDEF") & " : expected" & LF & to_string(bv_to_slv(bvVar)) & " : actual" severity error; assert (bv_to_slv(x"123456789ABCDEF") = x"0123456789ABCDEF") -- 123456789ABCDEF = 123456790123455 report "bv_to_slv_test error # 2 " & LF & to_string(x"0123456789ABCDEF") & " : expected" & LF & to_string(bv_to_slv(x"123456789ABCDEF")) & " : actual" severity error; wait; end process; --function cdft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_down_for_time2_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cdft("8 ms ","1 kHz") = slvVar) report "count_down_for_time2_test error # 1 " & LF & to_string("0111") & " : expected" & LF & to_string(cdft("8 ms ","1 kHz")) & " : actual" severity error; assert (cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz")) = "0110") report "count_down_for_time2_test error # 2 " & LF & to_string("0110") & " : expected" & LF & to_string(cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz"))) & " : actual" severity error; assert (cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz"))'length = 4) report "count_down_for_time2_test error # 3 " & LF & to_string(4) & " : expected" & LF & to_string(cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz"))'length) & " : actual" severity error; wait; end process; --function cdft(timeStrVal : string; -- freqStrVal : string; -- natVal : natural) return std_logic_vector; -- count for the time specified (minus a count of 2 for latency) using the frequency (or period) value passed as a reference and the natural value passed as a length for the vector (if it will fit in a vector that size) --function cdfth(timeStrVal : string; -- freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference count_down_for_time_high_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cdfth("1 us ","1E-15 yHz") = 10) report "count_down_for_time_high_test error # 1 " & LF & to_string(10) & " : expected" & LF & to_string(cdfth("1 us ","1E-15 yHz")) & " : actual" severity error; assert (cdfth("8 ms ","1 kHz") = 3) report "count_down_for_time_high_test error # 2 " & LF & to_string(3) & " : expected" & LF & to_string(cdfth("8 ms ","1 kHz")) & " : actual" severity error; wait; end process; --function ceil(RealVal : in real ) return real; -- rounds a real value up the the next highest real integer ceil_test : process begin assert (ceil(-9.999999) = -9.0) report "ceil_test error # 1 " & LF & to_string(-9.0) & " : expected" & LF & to_string(ceil(-9.999999)) & " : actual" severity error; assert (ceil(9.999999) = 10.0) report "ceil_test error # 2 " & LF & to_string(10.0) & " : expected" & LF & to_string(ceil(9.999999)) & " : actual" severity error; wait; end process; --function cfi(intVal : integer) return natural; cfi_test : process begin assert (cfi(-1000) = 5) report "cfi_test error # 1 " & LF & "5 : expected" & LF & to_string(cfi(-1000)) & " : actual" severity error; assert (cfi(-10000) = 6) report "cfi_test error # 2 " & LF & "6 : expected" & LF & to_string(cfi(-10000)) & " : actual" severity error; assert (cfi(1000) = 4) report "cfi_test error # 3 " & LF & "4 : expected" & LF & to_string(cfi(1000)) & " : actual" severity error; assert (cfi(-100_000) = 7) report "cfi_test error # 4 " & LF & "7 : expected" & LF & to_string(cfi(-100_000)) & " : actual" severity error; assert (cfi(100_000) = 6) report "cfi_test error # 5 " & LF & "6 : expected" & LF & to_string(cfi(100_000)) & " : actual" severity error; assert (cfi(-9999999) = report "cfi_test error # 6 " & LF & to_string( & " : expected" & LF &to_string(cfi(-9999999)) & " : actual" severity error; assert (cfi(9999999) = 7) report "cfi_test error # 7 " & LF & to_string(7) & " : expected" & LF & to_string(cfi(9999999)) & " : actual" severity error; wait; end process; --function cft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_for_time_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(20 downto 0); begin assert (cft(CNTTIME,SYSCLKFREQ) = "100111010101101100110100000000") report "count_for_time_test error # 1 " & LF & to_string("100111010101101100110100000000") & " : expected" & LF & to_string(cft(CNTTIME,SYSCLKFREQ)) & " : actual" severity error; assert (cft("1 min","66MHz") = "11101100000010001100111000000000") report "count_for_time_test error # 2 " & LF & to_string("11101100000010001100111000000000") & " : expected" & LF & to_string(cft("1 min","66MHz")) & " : actual" severity error; assert (cft("1 hr","66MHz") = "11011101010010000100000100100000000000") report "count_for_time_test error # 3 " & LF & to_string("11011101010010000100000100100000000000" ) & " : expected" & LF & to_string(cft("1 hr","66MHz")) & " : actual" severity error; assert (cft("1 day","66MHz") = "01010010111110110001100001101100000000000000" ) report "count_for_time_test error # 4 " & LF & to_string("010100101111101100011000011011000000000 00000") & " : expected" & LF & to_string(cft("1 day","66MHz")) & " : actual" severity error; assert (cft("1 day","66MHz")+cft("1 hr","66MHz")+cft("1 min","66MHz")+cft("1 sec","66MHz")+cft("1 ms","66MHz")+cft("1 us","66MHz")+cft("1 ns","66MHz")+cft("1 ps","66MHz")+cft("1 fs","66MHz") = "01010110011111110011100011111110110010010010" ) report "count_for_time_test error # 5 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 day","66MHz")+cft("1 hr","66MHz")+cft("1 min","66MHz")+cft("1 sec","66MHz")+cft("1 ms","66MHz")+cft("1 us","66MHz")+cft("1 ns","66MHz")+cft("1 ps","66MHz")+cft("1 fs","66MHz")) & " : actual" & LF & to_string(cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs","66MHz")) & " : actual" severity error; assert (cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs","66MHz") = "01010110011111110011100011111110110010010010" ) report "count_for_time_test error # 6 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 day","66MHz")+cft("1 hr","66MHz")+cft("1 min","66MHz")+cft("1 sec","66MHz")+cft("1 ms","66MHz")+cft("1 us","66MHz")+cft("1 ns","66MHz")+cft("1 ps","66MHz")+cft("1 fs","66MHz")+cft("1 as","66MHz")+cft("1 zs","66MHz")+cft("1 ys","66MHz")) & " : actual" & LF & to_string(cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz")) & " : actual" severity error; assert (cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz") = "01010110011111110011100011111110110010010010" ) report "count_for_time_test error # 7 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz")) & " : actual" severity error; assert (cft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz") = "0111000111001100111101101010001010110100000001010 01") report "count_for_time_test error # 8 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz")) & " : actual" severity error; assert (cft("1 sec","1E-3 kHz") = "01") report "count_for_time_test error # 9 " & LF & to_string("01") & " : expected" & LF & to_string(cft("1 sec","1E-3 kHz")) & " : actual" severity error; assert (cft("1 sec","1E-18 eHz") = "01") report "count_for_time_test error # 10 " & LF & to_string("01") & " : expected" & LF & to_string(cft("1 sec","1E-18 eHz")) & " : actual" severity error; assert (cft("1 ns ","1E-15 yHz") = "01") report "count_for_time_test error # 11 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 ns ","1E-15 yHz")) & " : actual" severity error; assert (cft("1 us ","1E-15 yHz") = "01111101000") report "count_for_time_test error # 12 " & LF & to_string("01111101000") & " : expected" & LF & to_string(cft("1 us ","1E-15 yHz")) & " : actual" severity error; slvVar := ext(cft("20 ms ","50 MHz"),21); assert (ext(cft("20 ms ","50 MHz"),21) = "011110100001001000000") report "count_for_time_test error # 13 " & LF & to_string("01111101000") & " : expected" & LF & to_string(ext(cft("20 ms ","50 MHz"),21)) & " : actual" severity error; wait; end process; --function cfth(timeStrVal : string; -- freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference count_for_time_high_test : process begin assert (cfth("1 us ","1E-15 yHz") = 10) report "count_for_time_high_test error # 1 " & LF & to_string(10) & " : expected" & LF & to_string(cfth("1 us ","1E-15 yHz")) & " : actual" severity error; wait; end process; --function cfth(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_for_time_high_test2 : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cfth("8 ms ","1 kHz") = 4) report "count_for_time_high_test2 error # 1 " & LF & to_string(4) & " : expected" & LF & to_string(cfth("8 ms ","1 kHz")) & " : actual" severity error; wait; end process; --function clkcnt(freq1StrVal : string; -- freq2StrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference clock_count_test : process begin assert (clkcnt("1 kHz","50 MHz") = "110000110100111") report "clock_count_test error # 1 " & LF & to_string("110000110100111") & " : expected" & LF & to_string(clkcnt("1 kHz","50 MHz")) & " : actual" severity error; wait; end process; --function conv_to_hex(vectorVal : bit_vector) return string; -- bit_vector to hexadecimal conversion conv_to_hex_test1 : process variable testVar : bit_vector(63 downto 0) := x"0123456789ABCDEF"; begin assert (conv_to_hex(testVar) = "0123456789ABCDEF") report "conv_to_hex_test1 error # 1 " & LF & "0123456789ABCDEF" & " : expected" & LF & conv_to_hex(testVar) & " : actual" severity error; wait; end process; --function conv_to_hex(vectorVal : std_logic_vector) return string; -- std_logic_vector to hexadecimal conversion conv_to_hex_test2 : process variable testVar : std_logic_vector(63 downto 0) := x"0123456789ABCDEF"; begin assert (conv_to_hex(testVar) = "0123456789ABCDEF") report "conv_to_hex_test2 error # 1 " & LF & "0123456789ABCDEF" & " : expected" & LF & conv_to_hex(testVar) & " : actual" severity error; wait; end process; --function conv_to_hex(vectorVal : std_ulogic_vector) return string; -- std_ulogic_vector to hexadecimal conversion conv_to_hex_test3 : process variable testVar : std_logic_vector(63 downto 0) := x"0123456789ABCDEF"; begin assert (conv_to_hex(testVar) = "0123456789ABCDEF") report "conv_to_hex_test3 error # 1 " & LF & "0123456789ABCDEF" & " : expected" & LF & conv_to_hex(testVar) & " : actual" severity error; wait; end process; --function cslv(int1Val : integer; -- int2Val : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" -- repackaged functions not tested --function cslv(sigVal : signed; -- intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" -- repackaged functions not tested --function cslv(usgVal : unsigned; -- intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" -- repackaged functions not tested --function cuft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_up_for_time_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(20 downto 0); begin assert (cuft(CNTTIME,SYSCLKFREQ) = "100111010101101100110011111111") report "count_up_for_time_test error # 1 " & LF & to_string("100111010101101100110011111111") & " : expected" & LF & to_string(cuft(CNTTIME,SYSCLKFREQ)) & " : actual" severity error; assert (cuft("1 min","66MHz") = "11101100000010001100110111111111") report "count_for_time_test error # 2 " & LF & to_string("11101100000010001100110111111111") & " : expected" & LF & to_string(cuft("1 min","66MHz")) & " : actual" severity error; assert (cuft("1 hr","66MHz") = "11011101010010000100000100011111111111") report "count_up_for_time_test error # 3 " & LF & to_string("11011101010010000100000100011111111111" ) & " : expected" & LF & to_string(cuft("1 hr","66MHz")) & " : actual" severity error; assert (cuft("1 day","66MHz") = "1010010111110110001100001101011111111111111") report "count_up_for_time_test error # 4 " & LF & to_string("101001011111011000110000110101111111111 1111") & " : expected" & LF & to_string(cuft("1 day","66MHz")) & " : actual" severity error; assert (cuft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs","66MHz") = "1010110011111110011100011111110110010010001") report "count_up_for_time_test error # 6 " & LF & to_string("101011001111111001110001111111011001001 0001") & " : expected" & LF & to_string(cuft("1 day","66MHz")+cuft("1 hr","66MHz")+cuft("1 min","66MHz")+cuft("1 sec","66MHz")+cuft("1 ms","66MHz")+cuft("1 us","66MHz")+cuft("1 ns","66MHz")+cuft("1 ps","66MHz")+cuft("1 fs","66MHz")+cuft("1 as","66MHz")+cuft("1 zs","66MHz")+cuft("1 ys","66MHz")) & " : actual" & LF & to_string(cuft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz")) & " : actual" severity error; assert (cuft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz") = "1110001110011001111011010100010101101000000010100 0") report "count_up_for_time_test error # 8 " & LF & to_string("111000111001100111101101010001010110100 00000101000") & " : expected" & LF & to_string(cuft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz")) & " : actual" severity error; assert (cuft("1 sec","1E-3 kHz") = "0") report "count_up_for_time_test error # 9 " & LF & to_string("00") & " : expected" & LF & to_string(cuft("1 sec","1E-3 kHz")) & " : actual" severity error; assert (cuft("1 sec","1E-18 eHz") = "0") report "count_up_for_time_test error # 10 " & LF & to_string("00") & " : expected" & LF & to_string(cuft("1 sec","1E-18 eHz")) & " : actual" severity error; assert (cuft("1 ns ","1E-15 yHz") = "0") report "count_up_for_time_test error # 11 " & LF & to_string("0") & " : expected" & LF & to_string(cuft("1 ns ","1E-15 yHz")) & " : actual" severity error; assert (cuft("1 us ","1E-15 yHz") = "1111100111") report "count_up_for_time_test error # 12 " & LF & to_string("1111100111") & " : expected" & LF & to_string(cuft("1 us ","1E-15 yHz")) & " : actual" severity error; slvVar := ext(cuft("20 ms ","50 MHz"),21); assert (ext(cuft("20 ms ","50 MHz"),25) = "0000011110100001000111111") report "count_up_for_time_test error # 13 " & LF & to_string("0000011110100001000111111") & " : expected" & LF & to_string(ext(cuft("20 ms ","50 MHz"),25)) & " : actual" severity error; wait; end process; --function cufth(timeStrVal : string; -- freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference count_up_for_time_high_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cufth("1 us ","1E-15 yHz") = 9) report "count_up_for_time_high_test error # 1 " & LF & to_string(9) & " : expected" & LF & to_string(cufth("1 us ","1E-15 yHz")) & " : actual" severity error; assert (cufth("8 ms ","1 kHz") = 2) report "count_up_for_time_high_test2 error # 1 " & LF & to_string(2) & " : expected" & LF & to_string(cufth("8 ms ","1 kHz")) & " : actual" severity error; wait; end process; --function dpfi(intVal : integer) return natural; -- returns the number of decimal places for an integer value --function dpfi_syn(intVal : integer) return natural; -- returns the number of decimal places for an integer value --function dpfr(realVal : real) return natural; -- returns the number of decimal places to the left of the decimal point for a real value --function dpfslvr(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the full range of the std_logic_vector passed --function dpfslvv(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the value of the std_logic_vector passed --function eq(vector1Val : std_logic_vector; -- vector2Val : std_logic_vector) return boolean; -- equality check function that is sensitive to vector length --function ext2(vectorVal : std_logic_vector; -- natVal : natural) return std_logic_vector; -- returns a standard logic vector, padded with zeros, to the length specified by intVal unless the vector is already longer than that ext_test : process constant slvVar : std_logic_vector := "0111"; variable slv1Var : std_logic_vector(11 downto 0); variable slv2Var : std_logic_vector(11 downto 0); variable slv3Var : std_logic_vector(slv1Var'range); begin slv1Var := ext2(int_to_slv(1000),slv1Var'length); slv2Var := ext2(int_to_slv(6),slv2Var'length); assert (ext2(slvVar,7) = "0000111") -- 7 bits report "ext_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string(ext2(slvVar,7)) & " : actual" severity error; assert (ext2(slvVar,4) = "0111") -- 4 bits report "ext_test error # 2 " & LF & to_string("0000111") & " : expected" & LF & to_string(ext2(slvVar,4)) & " : actual" severity error; assert (ext2(slvVar,4)'length = 4) -- 4 bits report "ext_test error # 3 " & LF & to_string(4) & " : expected" & LF & to_string(ext2(slvVar,4)'length) & " : actual" severity error; wait; end process; --function flip(vectorVal : bit_vector) return bit_vector; -- returns a bit_vector with all the bits in the reverse order --function flip(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector with all the bits in the reverse order --function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector; -- returns a std_ulogic_vector with all the bits in the reverse order --function floor(RealVal : in real ) return real; -- rounds a real value down the the next lowest real integer floor_test : process begin assert (floor(-9.999999) = -10.0) report "floor_test error # 1 " & LF & to_string(-10.0) & " : expected" & LF & to_string(floor(-9.999999)) & " : actual" severity error; assert (floor(9.999999) = 9.0) report "floor_test error # 2 " & LF & to_string(9.0) & " : expected" & LF & to_string(floor(9.999999)) & " : actual" severity error; assert (integer(floor(real(4)/real(2)))-1 = 1) report "floor_test error # 3 " & LF & to_string(1) & " : expected" & LF & to_string(integer(floor(real(4)/real(2)))-1) & " : actual" severity error; wait; end process; --function hex_to_slv(stringVal : string) return std_logic_vector; -- converts a Hexadeximal string to a standard logic vector --function int_to_slv(intVal : integer) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the integer value passed int_to_slv_test : process begin assert (int_to_slv(1) = "01") report "int_to_slv_test error # 1 " & LF & to_string(01) & " : expected" & LF & to_string(int_to_slv(1)) & " : actual" severity error; assert (int_to_slv(0) = "0") report "int_to_slv_test error # 2 " & LF & to_string(0) & " : expected" & LF & to_string(int_to_slv(0)) & " : actual" severity error; assert (int_to_slv(0)'high = 0) report "int_to_slv_test error # 2a " & LF & to_string(0) & " : expected" & LF & to_string(int_to_slv(0)'high) & " : actual" severity error; assert (int_to_slv(-1) = "11") report "int_to_slv_test error # 3 " & LF & "11" & " : expected" & LF & to_string(int_to_slv(-1)) & " : actual" severity error; wait; end process; --function itoa(intVal : integer) return string; -- common integer to string conversion function --function lfsr(vectorVal : std_ulogic_vector) return std_logic; -- returns the input to a Linear Feedback Shift Register (LFSR) using x^6 + x^5 + x^3 + x^2 + 1 as the primitive feedback polynomial lfsr_test : process constant OUTPUT_FILE : string := LOG_PATH & "lfsr_test_logfile" & LOG_EXT; variable LogFileLine : line; file LogFile : text; --open write_mode is OUTPUT_FILE; variable FileStatus : file_open_status; type LFSRAccessType is access std_logic_vector; type SeedAccessType is access std_logic_vector; variable LFSRVar : LFSRAccessType; variable SeedVar : SeedAccessType; variable LFSRTestVar : std_logic_vector(7 downto 0); begin file_open(LogFile, external_name => OUTPUT_FILE, open_kind => write_mode); write(logFileLine, string'("LFSR Maximal repeats")); writeLine(LogFile,logFileLine); write(logFileLine, string'("length length? after")); writeLine(LogFile,logFileLine); write(logFileLine, string'("__________________________________")); writeLine(LogFile,logFileLine); for outrLoopVar in 2 to 2 loop LFSRVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop LFSRVar.all(loopVar) := '1'; end loop; SeedVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop SeedVar.all(loopVar) := '1'; end loop; for loopVar in 1 to (2**LFSRVar'length)+2 loop --write(logFileLine, "LFSR Value : " & to_string(LFSRVar.all)); --writeLine(LogFile,logFileLine); LFSRVar.all := lfsr(LFSRVar.all); if (LFSRVar.all = SeedVar.all and loopVar < (2**LFSRVar.all'length)-1 and loopVar /= 1) then write(logFileLine, to_string(LFSRVar.all'length) & " " & "No " & to_string(loopVar)); writeLine(LogFile,logFileLine); exit; elsif (LFSRVar.all = SeedVar.all) then write(logFileLine, to_string(LFSRVar.all'length) & " " & "Yes " & to_string(loopVar)); writeLine(LogFile,logFileLine); exit; end if; end loop; deallocate(LFSRVar); deallocate(SeedVar); end loop; file_close(LogFile); wait; end process; --function lfsr_cft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference and the seed value passed as a starting point lfsr_cft_test : process constant OUTPUT_FILE : string := LOG_PATH & "lfsr_cft_test_logfile" & LOG_EXT; variable LogFileLine : line; --file LogFile : text;-- open write_mode is OUTPUT_FILE; constant timeVar : string := "17 ns"; constant freqVar : string := "1 GHz"; variable LFSRVar : std_logic_vector(lfsr_cfth(timeVar,freqVar) downto 0); variable LFSRCompleteVar : std_logic_vector(LFSRVar'range); variable LFSRCountTime : time; variable LFSRCount : integer; variable LFSRCountPeriod : time; begin LFSRCompleteVar := lfsr_cft_piped(timeVar,freqVar); LFSRCountTime := 0 ns; LFSRCount := 0; LFSRCountPeriod := to_period(1 GHz); LFSRVar := (others => '1'); for loopVar in 1 to 25 loop if (LFSRVar = LFSRCompleteVar and LFSRCountTime /= 15 ns) then assert FALSE report "lfsr_cft_test error " & LF & timeVar & " : expected" & LF & to_string(LFSRCountTime) & " : actual" severity error; end if; LFSRVar := lfsr(LFSRVar); LFSRCountTime := LFSRCountTime + LFSRCountPeriod; LFSRCount := LFSRCount + 1; end loop; wait; end process; extension_pack_lfsr_constants_generator : process constant PACKAGE_NAME : string := "extension_pack_lfsr_constants"; constant CONSTANT_NAME : string := "lfsr_constants"; constant OUTPUT_FILE : string := SRC_PATH & PACKAGE_NAME & SRC_EXT; constant LowerBound : natural := LFSRLowerBound; -- lower vector width to generate the LFSR constants for (minimum of 2) constant UpperBound : natural := LFSRUpperBound; -- upper vector width to generate the LFSR constants for variable fileStatusVar : file_open_status := open_ok; variable LogFileLine : line; file LogFile : text; --open write_mode is OUTPUT_FILE; type LFSRAccessType is access std_logic_vector; type SeedAccessType is access std_logic_vector; variable LFSRVar : LFSRAccessType; variable SeedVar : SeedAccessType; variable LFSRTestVar : std_logic_vector(7 downto 0); begin file_open(fileStatusVar, LogFile, OUTPUT_FILE, write_mode); if (fileStatusVar = open_ok) then write(logFileLine, string'("library ieee;")); writeLine(LogFile,logFileLine); write(logFileLine, "use ieee.std_logic_1164.all;" & LF); writeLine(LogFile,logFileLine); write(logFileLine, "package " & PACKAGE_NAME & " is" & LF); writeLine(LogFile,logFileLine); for outrLoopVar in LowerBound to UpperBound loop LFSRVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop LFSRVar.all(loopVar) := '1'; end loop; SeedVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop SeedVar.all(loopVar) := '1'; end loop; write(logFileLine, "type " & CONSTANT_NAME & "_type" & to_string(outrLoopVar) & " is array(1 to " & to_string(2**outrLoopVar-1) & ") of std_logic_vector(" & to_string(LFSRVar.all'high) & " downto " & to_string(LFSRVar.all'low) & ");"); writeLine(LogFile,logFileLine); write(logFileLine, "constant " & CONSTANT_NAME & to_string(outrLoopVar) & " : " & CONSTANT_NAME & "_type" & to_string(outrLoopVar) &" :=("); writeLine(LogFile,logFileLine); for loopVar in 1 to (2**LFSRVar'length)+2 loop write(logFileLine, """" & to_string(LFSRVar.all) & """"); if (loopVar = (2**LFSRVar'length)-1) then write(logFileLine, ");" & LF); else write(logFileLine, string'(",")); end if; writeLine(LogFile,logFileLine); LFSRVar.all := lfsr(LFSRVar.all); if (LFSRVar.all = SeedVar.all and loopVar < (2**LFSRVar.all'length)-1 and loopVar /= 1) then exit; elsif (LFSRVar.all = SeedVar.all) then exit; end if; end loop; deallocate(LFSRVar); deallocate(SeedVar); end loop; write(logFileLine, string'("attribute lfsrArrayLength : integer;")); writeLine(LogFile,logFileLine); for loopVar in LowerBound to UpperBound loop write(logFileLine, "attribute lfsrArrayLength of " & CONSTANT_NAME & to_string(loopVar) & " : constant is " & to_string(loopVar) & ";"); writeLine(LogFile,logFileLine); end loop; write(logFileLine, LF & string'("type LFSRRecType is record")); writeLine(LogFile,logFileLine); for loopVar in LowerBound to UpperBound loop write(logFileLine, " \" & to_string(loopVar) & "\ : " & CONSTANT_NAME & "_type" & to_string(loopVar) & ";"); writeLine(LogFile,logFileLine); end loop; write(logFileLine, string'("end record LFSRRecType;") & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("constant lfsrRec : LFSRRecType :=(")); writeLine(LogFile,logFileLine); for loopVar in LowerBound to UpperBound loop write(logFileLine, CONSTANT_NAME & to_string(loopVar)); if (loopVar = UpperBound) then write(logFileLine, string'(");") & LF); else write(logFileLine, string'(",")); end if; writeLine(LogFile,logFileLine); end loop; write(logFileLine, string'("end " & PACKAGE_NAME & ";") & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("package body " & PACKAGE_NAME & " is")); writeLine(LogFile,logFileLine); write(logFileLine, string'("end " & PACKAGE_NAME & ";")); writeLine(LogFile,logFileLine); file_close(LogFile); elsif (fileStatusVar = status_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = status_error" & LF severity error; elsif (fileStatusVar = name_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = name_error" & LF severity error; elsif (fileStatusVar = mode_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = mode_error" & LF severity error; end if; wait; end process; extension_pack_lfsr_str_generator : process type LFSRAccessType is access std_logic_vector; type SeedAccessType is access std_logic_vector; file LogFile : text; --open write_mode is OUTPUT_FILE; constant PACKAGE_NAME : string := "extension_pack_lfsr_str_constants"; constant CONSTANT_NAME : string := "lfsr_str"; constant OUTPUT_FILE : string := SRC_PATH & PACKAGE_NAME & SRC_EXT; constant LowerBound : natural := LFSRLowerBound; -- lower vector width to generate the LFSR constants for (minimum of 2) constant UpperBound : natural := LFSRUpperBound; -- upper vector width to generate the LFSR constants for variable arrayDepth : integer := 0; variable fileStatusVar : file_open_status := open_ok; variable LFSRTestVar : std_logic_vector(7 downto 0); variable LFSRVar : LFSRAccessType; variable LogFileLine : line; variable SeedVar : SeedAccessType; begin file_open(fileStatusVar, LogFile, OUTPUT_FILE, write_mode); if (fileStatusVar = open_ok) then for loopVar in LowerBound to UpperBound loop arrayDepth := 2**loopVar-1 + arrayDepth; end loop; write(logFileLine, string'("library ieee;")); writeLine(LogFile,logFileLine); write(logFileLine, "use ieee.std_logic_1164.all;" & LF); writeLine(LogFile,logFileLine); write(logFileLine, "package " & PACKAGE_NAME & " is" & LF); writeLine(LogFile,logFileLine); write(logFileLine, "type " & CONSTANT_NAME & "_type" & " is array(1 to " & to_string(arrayDepth) & ") of string(1" & " to " & to_string(UpperBound) & ");"); writeLine(LogFile,logFileLine); write(logFileLine, "constant " & CONSTANT_NAME & " : " & CONSTANT_NAME & "_type :=("); writeLine(LogFile,logFileLine); for outrLoopVar in LowerBound to UpperBound loop LFSRVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop LFSRVar.all(loopVar) := '1'; end loop; SeedVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop SeedVar.all(loopVar) := '1'; end loop; for loopVar in 1 to (2**LFSRVar'length)-1 loop write(logFileLine, " " & """" & ext(to_string(LFSRVar.all),UpperBound) & """"); if (outrLoopVar = UpperBound and loopVar = (2**LFSRVar'length)-1) then write(logFileLine, string'(");") & LF); else write(logFileLine, string'(",")); end if; writeLine(LogFile,logFileLine); LFSRVar.all := lfsr(LFSRVar.all); if (LFSRVar.all = SeedVar.all and loopVar < (2**LFSRVar.all'length)-1 and loopVar /= 1) then exit; elsif (LFSRVar.all = SeedVar.all) then exit; end if; end loop; deallocate(LFSRVar); deallocate(SeedVar); end loop; writeLine(LogFile,logFileLine); write(logFileLine, string'("attribute lfsr_str_length_low : integer;")); writeLine(LogFile,logFileLine); write(logFileLine, "attribute lfsr_str_length_low of " & CONSTANT_NAME & " : constant is " & to_string(LowerBound) & ";" & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("attribute lfsr_str_length_high : integer;")); writeLine(LogFile,logFileLine); write(logFileLine, "attribute lfsr_str_length_high of " & CONSTANT_NAME & " : constant is " & to_string(UpperBound) & ";" & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("end " & PACKAGE_NAME & ";") & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("package body " & PACKAGE_NAME & " is")); writeLine(LogFile,logFileLine); write(logFileLine, string'("end " & PACKAGE_NAME & ";")); writeLine(LogFile,logFileLine); file_close(LogFile); elsif (fileStatusVar = status_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = status_error" & LF severity error; elsif (fileStatusVar = name_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = name_error" & LF severity error; elsif (fileStatusVar = mode_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = mode_error" & LF severity error; end if; wait; end process; --function mult_s(Multiplier : std_logic_vector; -- Multiplicand : std_logic_vector) return std_logic_vector; -- signed multiply signed_mult_test : process begin assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 1 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 2 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("000","011") = "000000") -- 0 report "mult_s error # 3 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("000","011")) & " : actual" severity error; assert (mult_s("011","000") = "000000") -- 0 report "mult_s error # 4 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("011","000")) & " : actual" severity error; assert (mult_s("000","101") = "000000") -- 0 report "mult_s error # 5 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("000","101")) & " : actual" severity error; assert (mult_s("101","000") = "000000") -- 0 report "mult_s error # 6 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("101","000")) & " : actual" severity error; assert (mult_s("011","101") = "110111") -- 3 * (-3) = -9 report "mult_s error # 7 " & LF & to_string("110111") & " : expected" & LF & to_string(mult_s("011","101")) & " : actual" severity error; assert (mult_s("011","100") = "110100") -- 3 * (-4) = -12 report "mult_s error # 8 " & LF & to_string("110100") & " : expected" & LF & to_string(mult_s("011","100")) & " : actual" severity error; assert (mult_s("101","101") = "001001") -- (-3) * (-3) = 9 report "mult_s error # 9 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("101","101")) & " : actual" severity error; assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 10 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 11 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("100","100") = "010000") -- -4 * -4 = 16 report "mult_s error # 11 " & LF & to_string("010000") & " : expected" & LF & to_string(mult_s("100","100")) & " : actual" severity error; wait; end process; --function mult_us(Multiplier : std_logic_vector; -- Multiplicand : std_logic_vector) return std_logic_vector; -- unsigned multiply unsigned_mult_test : process begin assert (mult_us("011","011") = "001001") -- 0 report "mult error # 1 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_us("011","011") = "001001") -- 0 report "mult error # 2 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_us("011","011")) & " : actual" severity error; assert (mult_us("000","011") = "000000") -- 0 report "mult error # 3 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("000","011")) & " : actual" severity error; assert (mult_us("011","000") = "000000") -- 0 report "mult error # 4 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("011","000")) & " : actual" severity error; assert (mult_us("000","101") = "000000") -- 0 report "mult error # 5 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("000","101")) & " : actual" severity error; assert (mult_us("101","000") = "000000") -- 0 report "mult error # 6 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("101","000")) & " : actual" severity error; assert (mult_us("011","011") = "001001") -- 0 report "mult error # 7 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_us("011","011")) & " : actual" severity error; wait; end process; --function nat_to_slv(natVal : natural) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the natural value passed --function neg(VectorVal : std_logic_vector) return std_logic_vector; -- returns the negated value --function now return string; -- returns a string representation of the current simulation time now_test : process begin wait for 3 sec; assert (now = time'image(now)) report "now_test error # 1 " & LF & time'image(now) & " : expected" & LF & now & " : actual" severity error; wait; end process; --function reduce(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed reduce_test : process begin assert (reduce("00000") = "00") -- 0 report "reduce error # 1 " & LF & to_string("11") & " : expected" & LF & to_string(reduce("00000")) & " : actual" severity error; assert (reduce("00001") = "01") -- 1 report "reduce error # 2 " & LF & "expected : " & to_string("01") & LF & "actual : " & to_string(reduce("00001")) severity error; assert (reduce("11111") = "11") -- -1 report "reduce error # 3 " & LF & "expected : " & to_string("11") & LF & "actual : " & to_string(reduce("11111")) severity error; assert (reduce("10000") = "10000") -- -16 report "reduce error # 4 " & LF & "expected : " & to_string("10000") & LF & "actual : " & to_string(reduce("10000")) severity error; wait; end process; --function reduce_high(vectorVal : std_logic_vector) return integer; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed --function reduce_high_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'high value of a vector just large enough to represent the standard logic vector value passed --function reduce_length(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed (including a sign bit) --function reduce_length_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed --function reduce_unsigned(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed --function seq(str1Val : string; -- str2Val : string) return boolean; --function shl(vectorVal : std_logic_vector; -- natVal : natural) return std_logic_vector; --function slv_to_bcd(vectorVal : std_logic_vector; -- BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified --function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed --function slv_to_bcd_pipe(BCD_RVal : std_logic_vector; -- MSB_Val : std_logic; -- BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value --function str_to_int(stringVal : string) return integer; -- converts an Integer string to an integer str_to_int_test : process variable intVar : integer; begin intVar := str_to_int("10"); -- 3210 assert (intVar = 10) report "str_to_int_test error # 1 " & LF & "expected : 10" & LF & "actual : " & to_string(intVar) severity error; intVar := str_to_int("E-10 sec"); -- 3210 assert (intVar = -10) report "str_to_int_test error # 2 " & LF & "expected : -10" & LF & "actual : " & to_string(intVar) severity error; intVar := str_to_int("E-6 sec"); -- 3210 assert (intVar = -6) report "str_to_int_test error # 3 " & LF & "expected : -6" & LF & "actual : " & to_string(intVar) severity error; wait; end process; --function str_to_led(stringVal : string; -- CAVal : boolean) return std_logic_vector; -- converts a Hexadecimal string of any length to a std_logic_vector for seven segment LEDs --function strval_to_slv(stringVal : string) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector strval_to_slv_test : process begin assert (strval_to_slv("1") = "01") -- 0 report "bcd_to_led_test error # 1 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1")) & " : actual" severity error; assert (strval_to_slv("0") = "0") -- 0 report "bcd_to_led_test error # 1 " & LF & to_string("00") & " : expected" & LF & to_string(strval_to_slv("0")) & " : actual" severity error; assert (strval_to_slv("-1") = "11") -- -1 report "bcd_to_led_test error # 1 " & LF & to_string("11") & " : expected" & LF & to_string(strval_to_slv("-1")) & " : actual" severity error; assert (strval_to_slv("10 us") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 1 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv("10 us")) severity error; assert (strval_to_slv(" 10 us") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 2 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10 us")) severity error; assert (strval_to_slv(" 10 us ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 3 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10 us ")) severity error; assert (strval_to_slv(" 10.0 us ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 4 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10.0 us ")) severity error; assert (strval_to_slv(" 0.0100 ms ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 5 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.0100 ms ")) severity error; assert (strval_to_slv(" 0.0000100sec ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 6 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.0000100sec ")) severity error; assert (strval_to_slv(" 10E-6 sec ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 6a " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10E-6 sec ")) severity error; assert (strval_to_slv(" 10,000,000,000 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 7 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10,000,000,000 ")) severity error; assert (strval_to_slv(" 100,000Hz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 8 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100,000Hz ")) severity error; assert (strval_to_slv(" 100kHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 9 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100kHz ")) severity error; assert (strval_to_slv(" 0.1MHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 9a " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.1MHz ")) severity error; assert (strval_to_slv(" .1 MHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 9b " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" .1 MHz ")) severity error; assert (strval_to_slv(" 0.0001GHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 10 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.0001GHz ")) severity error; assert (strval_to_slv(" 10E 9 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 11 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10E 9 ")) severity error; assert (strval_to_slv(" 10E+9 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 12 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10E+9 ")) severity error; assert (strval_to_slv(" 10.0000000E+9 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 13 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10.0000000E+9 ")) severity error; assert (strval_to_slv(" 10.0000000E+9.000 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 13b " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10.0000000E+9.000 ")) severity error; assert (strval_to_slv(" 100E+3 HZ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 14 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ")) severity error; assert (strval_to_slv(" 1") = "01") report "strval_to_slv_test error # 15a " & LF & "expected : " & to_string("01") & LF & "actual : " & to_string(strval_to_slv(" 1")) severity error; assert (strval_to_slv(" -1") = "11") report "strval_to_slv_test error # 15b " & LF & "expected : " & to_string("11") & LF & "actual : " & to_string(strval_to_slv(" -1")) severity error; assert (strval_to_slv("1") = "01") report "strval_to_slv_test error # 16 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1")) & " : actual" severity error; assert (strval_to_slv("10") = "01010") report "strval_to_slv_test error # 17 " & LF & to_string("01010") & " : expected" & LF & to_string(strval_to_slv("10")) & " : actual" severity error; assert (strval_to_slv(" 100E+3 HZ ps ns MHz") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 18 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ")) severity error; assert (strval_to_slv(" 100E+3 HZ Hz") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 19 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ")) severity error; assert (strval_to_slv(" 100,000 HZ 234sec") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 20 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ 234sec")) severity error; assert (strval_to_slv("1 day") = "0100101011110000101001110110001110111011000111000 0000000000000000000") -- 0 report "strval_to_slv_test error # 21 " & LF & to_string("010010101111000010100111011000111011101 10001110000000000000000000000") & " : expected" & LF & to_string(strval_to_slv("1 day")) & " : actual" severity error; assert (strval_to_slv("1 hr") = "0110001111101011100010011101101001001110110100000 00000000000000") -- 0 report "strval_to_slv_test error # 22 " & LF & to_string("011000111110101110001001110110100100111 011010000000000000000000") & " : expected" & LF & to_string(strval_to_slv("1 hr")) & " : actual" severity error; assert (strval_to_slv("1 min") = "0110101010010100110101110100111101000011000000000 00000000") -- 0 report "strval_to_slv_test error # 23 " & LF & to_string("011010101001010011010111010011110100001 100000000000000000") & " : expected" & LF & to_string(strval_to_slv("1 min")) & " : actual" severity error; assert (strval_to_slv("1 sec") = "0111000110101111110101001001100011010000000000000 00") -- 0 report "strval_to_slv_test error # 24 " & LF & to_string("011100011010111111010100100110001101000 000000000000") & " : expected" & LF & to_string(strval_to_slv("1 sec")) & " : actual" severity error; assert (strval_to_slv("1 ms") = "01110100011010100101001010001000000000000") -- 0 report "strval_to_slv_test error # 25 " & LF & to_string("011101000110101001010010100010000000000 00") & " : expected" & LF & to_string(strval_to_slv("1 ms")) & " : actual" severity error; assert (strval_to_slv("1 us") = "0111011100110101100101000000000") -- 0 report "strval_to_slv_test error # 26 " & LF & to_string("0111011100110101100101000000000") & " : expected" & LF & to_string(strval_to_slv("1 us")) & " : actual" severity error; assert (strval_to_slv("1 ns") = "011110100001001000000") -- 0 report "strval_to_slv_test error # 27 " & LF & to_string("011110100001001000000") & " : expected" & LF & to_string(strval_to_slv("1 ns")) & " : actual" severity error; assert (strval_to_slv("1 ps") = "01111101000") -- 0 report "strval_to_slv_test error # 28 " & LF & to_string("01111101000") & " : expected" & LF & to_string(strval_to_slv("1 ps")) & " : actual" severity error; assert (strval_to_slv("1 fs") = "01") -- 0 report "strval_to_slv_test error # 29 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1 fs")) & " : actual" severity error; assert (strval_to_slv("1 as",-24) = "011110100001001000000") -- 0 report "strval_to_slv_test error # 30 " & LF & to_string("011110100001001000000") & " : expected" & LF & to_string(strval_to_slv("1 as",-24)) & " : actual" severity error; assert (strval_to_slv("1 zs",-24) = "01111101000") -- 0 report "strval_to_slv_test error # 31 " & LF & to_string("01111101000") & " : expected" & LF & to_string(strval_to_slv("1 zs",-24)) & " : actual" severity error; assert (strval_to_slv("1 ys",-24) = "01") -- 0 report "strval_to_slv_test error # 32 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1 ys",-24)) & " : actual" severity error; assert (strval_to_slv("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs") = "0100111000011101100011110011001111110010110011000 0111010000000101001") -- 0 report "strval_to_slv_test error # 33 " & LF & to_string("010011100001110110001111001100111111001 01100110000111010000000101001") & " : expected" & LF & to_string(strval_to_slv("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs")) & " : actual" severity error; wait; end process; --function strval_to_slv_high(stringVal : string) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed --function strval_to_slv_var_base(stringVal : string; -- intVal : integer) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector using the time base passed --function strval_to_slv_var_base_high(stringVal : string; -- intVal : integer) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed using the timebase value --function strh(stringVal : string) return integer; sxt_test : process constant slvVar : std_logic_vector := "0111"; variable slv1Var : std_logic_vector(11 downto 0); variable slv2Var : std_logic_vector(11 downto 0); variable slv3Var : std_logic_vector(slv1Var'range); begin slv1Var := sxt2(int_to_slv(-1000),slv1Var'length); slv2Var := sxt2(int_to_slv(-6),slv2Var'length); assert (sxt2(slvVar,7) = "0000111") -- 7 bits report "sxt2_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string(sxt2(slvVar,7)) & " : actual" severity error; assert (sxt2(slvVar,4) = "0111") -- 4 bits report "sxt2_test error # 2 " & LF & to_string("0000111") & " : expected" & LF & to_string(sxt2(slvVar,4)) & " : actual" severity error; assert (sxt2("1001",7) = "1111001") -- 7 bits report "sxt2_test error # 3 " & LF & to_string("1111001") & " : expected" & LF & to_string(sxt2("1001",7)) & " : actual" severity error; assert (sxt2("00",7) = "0000000") -- 4 bits report "sxt2_test error # 4 " & LF & to_string("0000000") & " : expected" & LF & to_string(sxt2("00",7)) & " : actual" severity error; assert (sxt2("1001",4) = "1001") -- 7 bits report "sxt2_test error # 5 " & LF & to_string("1001") & " : expected" & LF & to_string(sxt2("1001",7)) & " : actual" severity error; wait; end process; --function to_int(vectorVal : std_logic_vector) return integer; -- repackaging of "conv_integer" function --function to_period(freqVal : frequency) return time; -- returns a one cycle period value for a given frequency --function to_string(intVal : integer) return string; -- returns a string value for an integer value passed to_string_test1 : process begin assert (to_string(2147000000) = "2147000000") report "to_string_test1 error # 1 " & LF & "2147000000" & " : expected" & LF & to_string(2147000000) & " : actual" severity error; assert (to_string(-2147000000) = "-2147000000") report "to_string_test1 error # 2 " & LF & "-2147000000" & " : expected" & LF & to_string(-2147000000) & " : actual" severity error; wait; end process; --function to_string(realVal : real) return string; -- returns a string value for an real value passed to_string_test2 : process begin assert (to_string(1.000000e+30 = "1.000000e+308")report "to_string_test2 error # 1 " & LF & "1.000000e+308" & " : expected" & LF & to_string(1.000000e+30 & " : actual"severity error; assert (to_string(1.000000e-30 = "1.000000e-308")report "to_string_test2 error # 2 " & LF & "1.000000e-308" & " : expected" & LF & to_string(1.000000e-30 & " : actual"severity error; assert (to_string(-1.000000e-30 = "-1.000000e-308")report "to_string_test2 error # 3 " & LF & "-1.000000e-308" & " : expected" & LF & to_string(-1.000000e-30 & " : actual"severity error; wait; end process; --function to_string(timeVal : time) return string; to_string_test3 : process begin assert (to_string(3 ns) = "3 ns") report "to_string_test3 error # 1 " & LF & "3 ns" & " : expected" & LF & to_string(3 ns) & " : actual" severity error; assert (to_string(2040 ns) = "2040 ns") report "to_string_test3 error # 2 " & LF & "2040 ns" & " : expected" & LF & to_string(2040 ns) & " : actual" severity error; wait; end process; --function to_string(vectorVal : std_logic_vector) return string; --function vhfi(intVal : integer) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the integer value passed. This assumes the rest of the range declaration of the vector will be "downto 0" --function vhfn(natVal : natural) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the natural value passed. This assumes the rest of the range declaration of the vector will be "downto 0" --function vlfi(intVal : integer) return natural; -- returns an integer representing the length of a vector needed to represent the integer value passed --function vlfn(natVal : natural) return natural; -- returns an integer representing the length of a vector needed to represent the natural value passed --function vrfi(intVal : integer) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the integer value passed --function vrfn(natVal : natural) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the natural value passed -------------------------------------------------------------------------------- ---- Procedure Declarations -------------------------------------------------------------------------------- ---- synopsys translate_off --procedure clkgen( -- constant clkFreqSig : in frequency; -- signal clkSig : out std_logic); -- --procedure clkgen( -- signal clkEnSig : in boolean; -- signal clkFreqSig : in frequency; -- signal clkSig : out std_logic); -- --procedure clkgen( -- signal clkEnSig : in boolean; -- signal clkPeriodSig : in time; -- constant clkDutySig : in real; -- signal clkResetSig : in boolean; -- signal clkSig : inout std_logic); -- --procedure clkgen( -- signal clkEnSig : in boolean; -- signal clkFreqSig : in frequency; -- constant clkDutySig : in real; -- signal clkResetSig : in boolean; -- signal clkSig : inout std_logic); ---- synopsys translate_on -- --procedure FF( -- signal Clk : in std_logic; -- signal Rst : in std_logic; -- signal D : in std_logic_vector; -- signal Q : out std_logic_vector); -- --procedure slv_to_bcd( -- signal BCD_RIn : in std_logic_vector; -- signal BinIn : in std_logic_vector; -- signal BinFBIn : in std_logic_vector; -- signal ClkIn : in std_logic; -- constant BCD_DigitsVal : in integer; -- signal EnIn : in std_logic; -- signal RstLowIn : in std_logic; -- signal BCD_ROut : out std_logic_vector; -- signal Bin_ROut : out std_logic_vector; -- signal DoneOut : out std_logic); --exp_test : process --variable timeBaseVar : std_logic_vector(500 downto 0); --variable lineVar : line; --begin -- timeBaseVar := ext("01",timeBaseVar'length); -- for loopVar in 1 to 50 loop -- timeBaseVar := timeBaseVar(timeBaseVar'high-4 downto 0) * "1010"; -- ---- write(lineVar,to_string(real(reduce_high(timeBaseV ar))/real(loopVar))); ---- write(lineVar,LF); -- assert FALSE -- report -- to_string(real(reduce_high(timeBaseVar))/real(loopVar)) & LF -- severity note; -- end loop; -- -- wait; --end process; --assert FALSE --report "THIS IS THE END OF SIMULATION" & LF --severity failure; ------------------------------------------------------------------------------ end behavioral; ------------------------------------------------------------------------------ -- end of extension_pack testbench -- synopsys translate_on -- vector -- width latency -- 1 to 2 1 -- 3 to 8 2 -- 9 to 32 3 -- 33 to 128 4 -- 129 to 512 5 -- 513 to 1024 6 library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity Pipelined_Comparator is generic(bus_width : integer); port( aIn : in std_logic_vector(bus_width-1 downto 0); bIn : in std_logic_vector(bus_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; eqOut : out std_logic); end Pipelined_Comparator; architecture rtl of Pipelined_Comparator is constant MAXCOMPARATORWIDTH : integer := 2; constant upperGenConst : integer := integer(floor(real(bus_width)/real(MAXCOMPARATORWIDTH)))-1; signal aSig : std_logic_vector(aIn'length-1 downto 0); signal bSig : std_logic_vector(aSig'range); component and_r generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_Out : out std_logic); end component; component comparator_r generic(bus_width : integer); port( aIn : in std_logic_vector(bus_width-1 downto 0); bIn : in std_logic_vector(bus_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; eqOut : out std_logic); end component; begin aSig <= aIn; bSig <= bIn; single_comparator_structure : if (bus_width <= MAXCOMPARATORWIDTH) generate begin U1 : comparator_r generic map(bus_width => MAXCOMPARATORWIDTH) port map( aIn => aSig, bIn => bSig, clkIn => clkIn, sysResetIn => sysResetIn, eqOut => eqOut); end generate single_comparator_structure; multiple_comparator_structure : if (bus_width > MAXCOMPARATORWIDTH) generate signal eqSig : std_logic_vector(integer(ceil(real(bus_width)/real(MAXCOMPARATORWIDTH)))-1 downto 0); -- bus for all the comparator outputs begin full_width_comparator_structure : for genLoopVar in 0 to upperGenConst generate begin U2 : comparator_r generic map(bus_width => MAXCOMPARATORWIDTH) port map( aIn => aSig(MAXCOMPARATORWIDTH*genLoopVar+MAXCOMPARATORWI DTH-1 downto MAXCOMPARATORWIDTH*genLoopVar), bIn => bSig(MAXCOMPARATORWIDTH*genLoopVar+MAXCOMPARATORWI DTH-1 downto MAXCOMPARATORWIDTH*genLoopVar), clkIn => clkIn, sysResetIn => sysResetIn, eqOut => eqSig(genLoopVar)); end generate full_width_comparator_structure; partial_width_comparator_structure : if ((bus_width mod MAXCOMPARATORWIDTH) /=0) and (bus_width /= 0) generate -- for any leftovers from the full-width comparator chain begin U3 : comparator_r generic map(bus_width => bus_width mod MAXCOMPARATORWIDTH) port map( aIn => aSig(aSig'high downto aSig'high - bus_width mod MAXCOMPARATORWIDTH + 1), bIn => bSig(bSig'high downto bSig'high - bus_width mod MAXCOMPARATORWIDTH + 1), clkIn => clkIn, sysResetIn => sysResetIn, eqOut => eqSig(eqSig'high)); end generate partial_width_comparator_structure; U4 : and_r generic map(and_width => eqSig'length) port map( and_In => eqSig, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => eqOut); end generate multiple_comparator_structure; end rtl; |
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library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity rec_and_r is generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_Out : out std_logic); end rec_and_r; architecture rtl of rec_and_r is constant MAXANDWIDTH : integer := 4; component and_r generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_Out : out std_logic); end component; begin single_and_structure : if (and_width <= MAXANDWIDTH) generate begin U1 : and_r generic map(and_width => and_width) port map( and_In => and_In, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Out); end generate single_and_structure; multiple_and_structure : if (and_width > MAXANDWIDTH) generate signal and_Sig : std_logic_vector(integer(ceil(real(and_width)/real(MAXANDWIDTH)))-1 downto 0); -- bus for all the registered and gate outputs begin full_width_and_structure : for genLoopVar in 0 to integer(floor(real(and_width)/real(MAXANDWIDTH)))-1 generate begin U1 : and_r generic map(and_width => MAXANDWIDTH) port map( and_In => and_In(MAXANDWIDTH*genLoopVar+MAXANDWIDTH-1 downto MAXANDWIDTH*genLoopVar), clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Sig(genLoopVar)); end generate full_width_and_structure; partial_width_and_structure : if ((and_width mod MAXANDWIDTH) /= 0) and (and_width /= 0) generate begin U2 : and_r generic map(and_width => and_width mod MAXANDWIDTH) port map( and_In => and_In(and_In'high downto and_In'high - and_width mod MAXANDWIDTH), clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Sig(and_Sig'high)); end generate partial_width_and_structure; recursive_and_structure : if and_Sig'length /= 1 generate begin U3 : and_r generic map(and_width => and_Sig'length) port map( and_In => and_Sig, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Out); end generate recursive_and_structure; end generate multiple_and_structure; end rtl; ------------------------------------------------------------------------------ -- -- author : Michael Bills () -- -- description : This package has functions and procedures -- for testbenching and assisting in RTL design -- creation. It consists mostly of conversion functions. -- This is a two-part package. The package testbench is -- included at the bottom begining around line 4560. -- -- -- -- -- Copyright (c) 2005 by Michael Bills -- -- Permission to use, copy, modify, distribute, and sell this source code -- for any purpose is hereby granted without fee, provided that -- the above copyright notices and this permission notice appear -- in all copies of this source code. -- -- THIS SOURCE CODE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND, -- EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, -- ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. -- -- THE USER OF THIS SOURCE CODE ASSUMES ALL LIABILITY FOR THEIR USE -- OF THIS SOURCE CODE. -- -- IN NO EVENT SHALL MICHAEL BILLS BE LIABLE FOR ANY SPECIAL, INCIDENTAL, -- INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER -- RESULTING FROM LOSS OF USE, DATA, OR PROFITS, WHETHER OR NOT ADVISED OF -- THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING -- OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. -- ------------------------------------------------------------------------------ -- LIBRARY STATEMENT library extension_lib, ieee; -- PACKAGE STATEMENT --use extension_lib.extension_pack_constants.all; --use extension_lib.extension_pack_lfsr_str_constants.al l; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed."abs"; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------ package extension_pack is ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- Type Declarations ------------------------------------------------------------------------------ type hexchar is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'); type hex is array (positive range <>) of hexchar; type LED_Char is (' ', '"', ''', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '=', '?', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'O', 'P', 'S', 'T', 'U', 'Y', 'Z', '\', ']', '^', '_', 'b', 'c', 'd', 'h', 'g', 'j', 'l', 'n', 'o', 'r', 'u', '¬', '*', '¯', '°', '·'); type SevenSegLED is array (positive range <>) of LED_Char; -- synopsys translate_off type frequency is range 1 to 2_147_483_647 units Hz; daHz = 10 Hz; -- dekahertz 10E+1 hHz = 10 daHz; -- hectohertz 10E+2 kHz = 10 hHz; -- kilohertz 10E+3 MHz = 1000 kHz; -- megahertz 10E+6 GHz = 1000 MHz; -- gigahertz 10E+9 end units; -- synopsys translate_on ------------------------------------------------------------------------------ -- Subtype Declarations ------------------------------------------------------------------------------ --subtype bv is bit_vector; --subtype char is character; ---- synopsys translate_off --subtype fok is file_open_kind; --subtype fos is file_open_status; --subtype freq is frequency; ---- synopsys translate_on --subtype int is integer; --subtype nat is natural; --subtype pos is positive; --subtype sl is std_logic; --subtype slv is std_logic_vector; --subtype str is string; --subtype sul is std_ulogic; --subtype sulv is std_ulogic_vector; --subtype uns is unsigned; ------------------------------------------------------------------------------ -- Constant Declarations ------------------------------------------------------------------------------ -- count_for_time base size, that is to say, the smallest time value -- that is used for this function. (-60 means the timebase = 10E-60 seconds). -- VHDL uses a "timebase" or base unit of 1 fs (time'pos(1 fs) = 1) -- this value should be increased if round off error occurs -- in a value computed by the function "count_for_time" or if -- array length errors similar to this occur: -- # ** Fatal: (vsim-3420) Array lengths do not match. Left is (96 downto 0). Right is (97 downto 0). -- -- This value must be smaller than MAX_VECT_SIZE by a factor of 4 for -- logic vectors 2 bits long and it must be smaller by a factor of 3.5 for -- logic vectors longer than 2 bits constant CFT_BASE_SIZE : integer := -27; -- this value represents the largest size a logic vector may be for certain -- functions and procedures in this package. It is used to set upper loop -- limits for non-deterministic values thus avoiding the use of access -- types and enabling the functions to be used for synthesizeable code. -- -- This value may be increased (as high as natural'high will allow) -- if a larger value needs to be represented, or it may be decreased -- if compile time is excessive by modifying the CFT_BASE_SIZE constant constant MAX_VECT_SIZE : natural := (-CFT_BASE_SIZE)*4; constant LOG_PATH : string := "../../logs/"; -- location to place log files constant LOG_EXT : string := ".txt"; -- log file extention constant SRC_PATH : string := "../../src/"; -- location to access/place VHDL source files constant SRC_EXT : string := ".vhd"; -- VHDL source file extension -- LFSR pre-computed constant package width bounds constant LFSRLowerBound : integer := 2; constant LFSRUpperBound : integer := 12; type LFSR_Polynomial_Exponents_type is array(2 to 16 of string(1 to 20);-- http://direct.xilinx.com/bvdocs/appnotes/xapp052.pdf -- must be both primitive and prime to give a sequence of lenth 2**N-1 constant LFSR_Polynomial_Exponents : LFSR_Polynomial_Exponents_type :=( "2,1 ","3,2 ","4,3 ","5,3 ","6,5 ","7,6 ","8,6,5,4 ","9,5 ","10,7 ", "11,9 ","12,6,4,1 ","13,4,3,1 ","14,5,3,1 ","15,14 ","16,15,13,4 ","17,14 ","18,11 ","19,6,2,1 ","20,17 ", "21,19 ","22,21 ","23,18 ","24,23,22,17 ","25,22 ","26,6,2,1 ","27,5,2,1 ","28,25 ","29,27 ","30,6,4,1 ", "31,28 ","32,22,2,1 ","33,20 ","34,27,2,1 ","35,33 ","36,25 ","37,5,4,3,2,1 ","38,6,5,1 ","39,35 ","40,38,21,19 ", "41,38 ","42,41,20,19 ","43,42,38,37 ","44,43,18,17 ","45,44,42,41 ","46,45,26,25 ","47,42 ","48,47,21,20 ","49,40 ","50,49,24,23 ", "51,50,36,35 ","52,49 ","53,52,38,37 ","54,53,18,17 ","55,31 ","56,55,35,34 ","57,50 ","58,39 ","59,58,38,37 ","60,59 ", "61,60,46,45 ","62,61,6,5 ","63,62 ","64,63,61,60 ","65,47 ","66,65,57,56 ","67,66,58,57 ","68,59 ","69,67,42,40 ","70,69,55,54 ", "71,65 ","72,66,25,19 ","73,48 ","74,73,59,58 ","75,74,65,64 ","76,75,41,40 ","77,76,47,46 ","78,77,59,58 ","79,70 ","80,79,43,42 ", "81,77 ","82,79,47,44 ","83,82,38,37 ","84,71 ","85,84,58,57 ","86,85,74,73 ","87,74 ","88,87,17,16 ","89,51 ","90,89,72,71 ", "91,90,8,7 ","92,91,80,79 ","93,91 ","94,73 ","95,84 ","96,94,49,47 ","97,91 ","98,87 ","99,97,54,52 ","100,63 ", "101,100,95,94 ","102,101,36,35 ","103,94 ","104,103,94,93 ","105,89 ","106,91 ","107,105,44,42 ","108,77 ","109,108,103,102 ","110,109,98,97 ", "111,101 ","112,110,69,67 ","113,104 ","114,113,33,32 ","115,114,101,100 ","116,115,46,45 ","117,115,99,97 ","118,85 ","119,111 ","120,113,9,2 ", "121,103 ","122,121,63,62 ","123,121 ","124,87 ","125,124,18,17 ","126,125,90,89 ","127,126 ","128,126,101,99 ","129,124 ","130,127 ", "131,130,84,83 ","132,103 ","133,132,82,81 ","134,77 ","135,124 ","136,135,11,10 ","137,116 ","138,137,131,130 ","139,136,134,131 ","140,111 ", "141,140,110,109 ","142,121 ","143,142,123,122 ","144,143,75,74 ","145,93 ","146,145,87,86 ","147,146,110,109 ","148,121 ","149,148,40,39 ","150,97 ", "151,148 ","152,151,87,86 ","153,152 ","154,152,27,25 ","155,154,124,123 ","156,155,41,40 ","157,156,131,130 ","158,157,132,131 ","159,128 ","160,159,142,141 ", "161,143 ","162,161,75,74 ","163,162,104,103 ","164,163,151,150 ","165,164,135,134 ","166,165,128,127 ","167,161 ","168,166,153,151 " ); ------------------------------------------------------------------------------ -- Function Declarations ------------------------------------------------------------------------------ function "*"(MultiplicandVal : integer; MultiplierVal : std_logic_vector) return std_logic_vector; function "*"(MultiplicandVal : std_logic_vector; MultiplierVal : integer) return std_logic_vector; function "/"(DividendVal : std_logic_vector; DivisorVal : std_logic_vector) return std_logic_vector; function "/"(DividendVal : std_logic_vector; DivisorVal : integer) return std_logic_vector; function "/"(DividendVal : string; DivisorVal : integer) return std_logic_vector; function bcd_to_led(slvVal : std_logic_vector ; CAVal : boolean) return std_logic_vector; -- binary coded decimal to seven segment LED conversion function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed function bcd_to_slv_pipe(BCD_RVal : std_logic_vector; BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector; -- repackaging of "To_StdLogicVector" function function cdft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified (minus a count of 2 for latency) using the frequency (or period) value passed as a reference function cdft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector; -- count for the time specified (minus a count of 2 for latency) using the frequency (or period) value passed as a reference and the natural value passed as a length for the vector (if it will fit in a vector that size) function cdfth(timeStrVal : string; freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified (minus a count of 2) using the frequency (or period) value passed as a reference function ceil(RealVal : in real) return real; -- rounds a real value up the the next highest real integer function cfi(intVal : integer) return natural; -- This function returns a natural representing the number of characters required to reprsent an integer value. It is essentially an integer'length function for the characters. function cft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference function cft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference and the integer value passed as a length for the vector (if it will fit in a vector that size) function cfth(timeStrVal : string; freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference function cftu(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference, return an unsigned std_logic_vector function cftu(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector; -- count for the time specified, plus (or minus) the fudge factor, using the frequency (or period) value passed as a reference, return an unsigned std_logic_vector function clkcnt(freq1StrVal : string; freq2StrVal : string) return std_logic_vector; -- create a 50% duty cycle count time using the frequency (or period) value passed as a reference function conv_to_hex(vectorVal : bit_vector) return string; -- bit_vector to hexadecimal conversion function conv_to_hex(vectorVal : std_logic_vector) return string; -- std_logic_vector to hexadecimal conversion function conv_to_hex(vectorVal : std_ulogic_vector) return string; -- std_ulogic_vector to hexadecimal conversion function crc16(serialInVal : std_logic; vectorVal : std_logic_vector) return std_logic_vector; -- returns the input to a Cyclic Redundancy Check (CRC) using the polynomial x^16 + x^15 + x^2 + 1. function cslv(int1Val : integer; int2Val : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" function cslv(sigVal : signed; intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" function cslv(usgVal : unsigned; intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" function cuft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- count for the time specified (minus a count of 1 for latency) using the frequency (or period) value passed as a reference function cuft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector; -- count for the time specified (minus a count of 1 for latency) using the frequency (or period) value passed as a reference and the integer value passed as a length for the vector (if it will fit in a vector that size) function cufth(timeStrVal : string; freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference function dpfi(intVal : integer) return natural; -- returns the number of decimal places for an integer value function dpfi_syn(intVal : integer) return natural; -- returns the number of decimal places for an integer value function dpfr(realVal : real) return natural; -- returns the number of decimal places to the left of the decimal point for a real value function dpfslvr(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the full range of the std_logic_vector passed function dpfslvv(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the value of the std_logic_vector passed function eq(vector1Val : std_logic_vector; vector2Val : std_logic_vector) return boolean; -- equality check function that is sensitive to vector length function ext(strVal : string; natVal : natural) return string; -- returns a string, padded with spaces, to the length specified by intVal unless the string is already longer than that function ext2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector; -- returns a standard logic vector, padded with zeros, to the length specified by intVal unless the vector is already longer than that function flip(vectorVal : bit_vector) return bit_vector; -- returns a bit_vector with all the bits in the reverse order function flip(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector with all the bits in the reverse order function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector; -- returns a std_ulogic_vector with all the bits in the reverse order function floor(RealVal : in real) return real; -- rounds a real value down the the next loweest real integer function hex_to_slv(stringVal : string) return std_logic_vector; -- converts a Hexadeximal string to a standard logic vector function int_to_slv(intVal : integer) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the integer value passed function itoa(intVal : integer) return string; -- common integer to string conversion function function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string; polynomialStrVal : string) return std_logic_vector; -- returns the input to a Linear Feedback Shift Register (LFSR) using the polynomial function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string) return std_logic_vector; -- returns the input to a Linear Feedback Shift Register (LFSR) using a primitive polynomial function lfsr(vectorVal : std_logic_vector) return std_logic_vector; -- returns the input to a Linear Feedback Shift Register (LFSR) using a primitive polynomial. This function defaults to Type 2 XOR feedback. function lfsr_cft(timeStrVal : string; freqStrVal : string; seedVal : std_logic_vector; lfsrTypeVal : string; fudgeStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified, plus (or minus) the fudge factor, using the frequency (or period) value passed as a reference and the seed value passed as a starting point function lfsr_cft(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified, plus (or minus) the fudge factor, using the frequency (or period) value passed as a reference function lfsr_cft(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference function lfsr_cft_piped(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference (for use in creating counters that have pipelined comparator stop value detection) function lfsr_cft_piped_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference (for use in creating counters that have pipelined comparator stop value detection), better suited for synthesis, (other function works also) function lfsr_cft_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference (for use in creating counters that have pipelined comparator stop value detection), better suited for synthesis, (other function works also) function lfsr_cfth(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return integer; -- repackaging of cfth for ease of lfsr use, plus (or minus) the fudge factor function lfsr_cfth(timeStrVal : string; freqStrVal : string) return integer; -- repackaging of cfth for ease of lfsr use function max(int1Val : integer; int2Val : integer) return integer; -- returns the maximum of the two values passed function mult_s(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector; -- signed multiply function mult_us(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector; -- unsigned multiply function nat_to_slv(natVal : natural) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the natural value passed function neg(VectorVal : std_logic_vector) return std_logic_vector; -- returns the negated value -- synopsys translate_off impure function now return string; -- returns a string representation of the current simulation time -- synopsys translate_on function pipelined_comparator_latency(busWidthVal : integer) return string; -- returns the latency value function pipelined_comparator_latency(timeStrVal : string; freqStrVal : string) return string; -- returns the latency value function reduce(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed (including a sign bit) function reduce_high(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'high value of a vector just large enough to represent the standard logic vector value passed (including a sign bit) function reduce_high_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'high value of a vector just large enough to represent the standard logic vector value passed function reduce_length(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed (including a sign bit) function reduce_length_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed function reduce_unsigned(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed function roundup(int1Val : integer; int2Val : integer) return integer; -- rounds an integer value up the the next higher multiple of the integer passed function rounddown(int1Val : integer; int2Val : integer) return integer; -- This function rounds the first integer value down to the next lower multiple of the second integer passed function seq(str1Val : string; str2Val : string) return boolean; function shl(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector; function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed function slv_to_bcd(vectorVal : std_logic_vector; BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified function slv_to_bcd_pipe(BCD_RVal : std_logic_vector; MSB_Val : std_logic; BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value function str_to_int(stringVal : string) return integer; -- converts an Integer string to an integer -- synopsys translate_off function str_to_line(strVal : string) return line; -- synopsys translate_on function str_to_led(stringVal : string; CAVal : boolean) return std_logic_vector; -- converts a Hexadecimal string of any length to a std_logic_vector for seven segment LEDs function str_to_slv(stringVal : string) return std_logic_vector; -- converts a string, of any length to a std_logic_vector function strh(stringVal : string) return integer; function strval_to_slv(stringVal : string) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector function strval_to_slv(stringVal : string; intVal : integer) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector using the time base passed function strval_to_slv_high(stringVal : string) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed function strval_to_slv_var_base_high(stringVal : string; intVal : integer) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed using the timebase value function sxt2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector; -- returns a standard logic vector, padded with sign bits, to the length specified by intVal unless the vector is already longer than that function to_int(vectorVal : std_logic_vector) return integer; -- repackaging of "conv_integer" function -- synopsys translate_off function to_period(freqVal : frequency) return time; -- returns a one cycle period value for a given frequency --function to_period(freqVal : string) return time; -- returns a one cycle period value for a given frequency -- synopsys translate_on function to_string(boolVal : boolean) return string; -- returns the string representation of a boolean value passed function to_string(intVal : integer) return string; -- returns the string representation of an integer value passed function to_string(realVal : real) return string; -- returns the string representation of a real value passed function to_string(timeVal : time) return string; -- returns the string representation of a time value passed function to_string(vectorVal : std_logic_vector) return string; -- returns the string representation of a std_logic_vector value passed function vhfi(intVal : integer) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the integer value passed. This assumes the rest of the range declaration of the vector will be "downto 0" function vhfn(natVal : natural) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the natural value passed. This assumes the rest of the range declaration of the vector will be "downto 0" function vlfi(intVal : integer) return natural; -- returns an integer representing the length of a vector needed to represent the integer value passed function vlfn(natVal : natural) return natural; -- returns an integer representing the length of a vector needed to represent the natural value passed function vrfi(intVal : integer) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the integer value passed function vrfn(natVal : natural) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the natural value passed function xnor_reduce(vectorVal : std_logic_vector) return std_logic; -- multiple input xnor gate function xor_reduce(vectorVal : std_logic_vector) return std_logic; -- multiple input xor gate ------------------------------------------------------------------------------ -- Procedure Declarations ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( constant clkFreqSig : in frequency; signal clkSig : out std_logic); procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; signal clkSig : out std_logic); procedure clkgen( signal clkEnSig : in boolean; signal clkPeriodSig : in time; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic); procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic); -- synopsys translate_on procedure FF( signal Clk : in std_logic; signal Rst : in std_logic; signal D : in std_logic_vector; signal Q : out std_logic_vector); procedure slv_to_bcd( signal BCD_RIn : in std_logic_vector; signal BinIn : in std_logic_vector; signal BinFBIn : in std_logic_vector; signal ClkIn : in std_logic; constant BCD_DigitsVal : in integer; signal EnIn : in std_logic; signal RstLowIn : in std_logic; signal BCD_ROut : out std_logic_vector; signal Bin_ROut : out std_logic_vector; signal DoneOut : out std_logic); ------------------------------------------------------------------------------ -- Aliases ------------------------------------------------------------------------------ -- synopsys translate_off alias bool is boolean; alias bv is bit_vector; alias char is character; alias fok is file_open_kind; alias fos is file_open_status; alias freq is frequency; alias int is integer; alias nat is natural; alias pos is positive; alias sl is std_logic; alias slv is std_logic_vector; alias str is string; alias sul is std_ulogic; alias sulv is std_ulogic_vector; alias uns is unsigned; -- synopsys translate_on ------------------------------------------------------------------------------ end extension_pack; ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ package body extension_pack is ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- Functions -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "*" -- -- DESCRIPTION : This function multiplies an integer by a -- std_logic_vector and returns a std_logic_vector -- -- NOTES : -- ------------------------------------------------------------------------------ function "*"(MultiplicandVal : integer; MultiplierVal : std_logic_vector) return std_logic_vector is begin return int_to_slv(MultiplicandVal)*MultiplierVal; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "*" -- -- DESCRIPTION : This function multiplies a std_logic_vector by an integer -- and returns a std_logic_vector -- -- NOTES : -- ------------------------------------------------------------------------------ function "*"(MultiplicandVal : std_logic_vector; MultiplierVal : integer) return std_logic_vector is begin return MultiplicandVal*int_to_slv(MultiplierVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "/" -- -- DESCRIPTION : This function divides an unsigned std_logic vector value -- by another unsigned std_logic_vector value and returns -- a std_logic_vector that is the same length -- as the dividend -- -- NOTES : the algorithm used in this function -- is the standard long division algorithm. -- it rounds to the nearest value -- ------------------------------------------------------------------------------ function "/"(DividendVal : std_logic_vector; DivisorVal : std_logic_vector) return std_logic_vector is variable DividendVar : std_logic_vector(DividendVal'length+DivisorVal'len gth downto 0); variable DivisorVar : std_logic_vector(DivisorVal'length downto 0); variable InterimVar : std_logic_vector(DivisorVal'length downto 0); variable ResultVar : std_logic_vector(DividendVal'length downto 0); begin DividendVar := ext(DividendVal & '0',DividendVar'length); DivisorVar := '0' & DivisorVal; InterimVar := '0' & DividendVar(DividendVar'high downto DividendVar'high-(DivisorVar'length-2)); ResultVar := (others => '0'); for loopVar in ResultVar'range loop if (InterimVar >= DivisorVar) then InterimVar := InterimVar - DivisorVar; InterimVar := InterimVar(InterimVar'high-1 downto 0) & DividendVar(loopVar); ResultVar(loopVar) := '1'; else InterimVar := InterimVar(InterimVar'high-1 downto 0) & DividendVar(loopVar); ResultVar(loopVar) := '0'; end if; end loop; -- round to the nearest digit if (InterimVar >= DivisorVal) then -- it the remainder is at least 1/2 of the Divisor (it was effectively multiplied by two during the final pass through the loop) ResultVar := ResultVar + '1'; -- then round up to the next value end if; return ResultVar(ResultVar'length-2 downto 0); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "/" -- -- DESCRIPTION : This function divides an unsigned std_logic_vector value -- by an integer value -- -- NOTES : -- ------------------------------------------------------------------------------ function "/"(DividendVal : std_logic_vector; DivisorVal : integer) return std_logic_vector is begin return DividendVal/int_to_slv(DivisorVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : "/" -- -- DESCRIPTION : This function divides an integer string value -- by an integer value -- -- NOTES : -- ------------------------------------------------------------------------------ function "/"(DividendVal : string; DivisorVal : integer) return std_logic_vector is begin return strval_to_slv(DividendVal)/int_to_slv(DivisorVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bcd_to_led -- -- DESCRIPTION : This function converts a packed BCD vector or a hex value -- into a seven segment LED output -- -- NOTES if the CAVal boolean input is true the output will -- be for a Common Anode (1=off) display, otherwise it will -- be for a Common Cathode (1=on)display. -- _____ -- | a | -- f| |b -- |_____| -- | g | -- e| |c -- |_____| -- d -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to -- ------------------------------------------------------------------------------ function bcd_to_led(slvVal : std_logic_vector ; CAVal : boolean) return std_logic_vector is variable resultVar : std_logic_vector(7*slvVal'length/4-1 downto 0); variable vectorParseVar : std_logic_vector(3 downto 0); variable vectorVar : std_logic_vector(slvVal'length-1 downto 0); begin vectorVar := slvVal; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to for loopVar in 0 to slvVal'length/4-1 loop vectorParseVar := vectorVar(4*loopVar+3 downto 4*loopVar); case vectorParseVar is -- Illuminated -- vector Segment -- value abcdefg when x"0" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111110"; -- 0 when x"1" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110000"; -- 1 when x"2" => resultVar(7*loopVar+6 downto 7*loopvar) := "1101101"; -- 2 when x"3" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111001"; -- 3 when x"4" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110011"; -- 4 when x"5" => resultVar(7*loopVar+6 downto 7*loopvar) := "1011011"; -- 5 when x"6" => resultVar(7*loopVar+6 downto 7*loopvar) := "1011111"; -- 6 when x"7" => resultVar(7*loopVar+6 downto 7*loopvar) := "1110010"; -- 7 when x"8" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111111"; -- 8 when x"9" => resultVar(7*loopVar+6 downto 7*loopvar) := "1110011"; -- 9 when x"A" => resultVar(7*loopVar+6 downto 7*loopvar) := "0001000"; -- A when x"B" => resultVar(7*loopVar+6 downto 7*loopvar) := "1100000"; -- b when x"C" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110001"; -- C when x"D" => resultVar(7*loopVar+6 downto 7*loopvar) := "1000010"; -- d when x"E" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110000"; -- E when x"F" => resultVar(7*loopVar+6 downto 7*loopvar) := "0111000"; -- F when others => end case; end loop; if (CAVal) then return not resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to else return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bcd_to_slv -- -- DESCRIPTION : This function converts a packed binary coded decimal (BCD) -- in standard logic vector for and returns an unsigned, -- decending range, binary value -- -- NOTES -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector is type BCDArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector of std_logic_vector(vectorVal'length-1 downto 0); -- variable CarryVar : std_logic_vector(vectorVal'length/4 downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if no carry to the next BCD Digit is needed variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if carry to the next BCD Digit is needed variable BCDVar : BCDArrayType; -- BCD value array variable ResultVar : std_logic_vector(vectorVal'length-1 downto 0); begin BCDVar(0) := vectorVal; -- set the initial entry in the array to the input vector for OutrLoopVar in 1 to vectorVal'length loop -- CarryVar(CarryVar'high) := '0'; for InnrLoopVar in CarryVar'high-1 downto 0 loop -- start at the MSB of the BCD vector BCD_WoCarVar := '0' & BCDVar(OutrLoopVar-1) -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to (4*InnrLoopVar+3 downto 4*InnrLoopVar+1); -- read the results of the previous calculation BCD_WiCarVar := BCD_WoCarVar + "0101"; -- compute the result for the current BCD digit if carry is needed CarryVar(InnrLoopVar) := BCDVar(OutrLoopVar-1)(4*InnrLoopVar); -- read in the next bit of the LSB of the previous BCD digit input into the lowest carry bit if (CarryVar(InnrLoopVar+1) = '1') then -- if the the previous digit has a carry bit then then the result of the binary shift right is greater by 5 BCDVar(OutrLoopVar)(4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar; else -- otherwise BCDVar(OutrLoopVar)(4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar; -- we shift the bits right by 1 space end if; end loop; ResultVar(OutrLoopVar-1) := BCDVar(OutrLoopVar-1)(0); end loop; return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bcd_to_slv_pipe -- -- DESCRIPTION : This function converts a packed binary coded decimal (BCD) -- into an unsigned, decending range, -- binary value into a standard logic vector -- and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it. -- it is for use in pipelined implementations where -- the binary coded decimal output is registered -- and passed back to the function along with the binary -- vector input to be shifted out of its MSB -- register and into the function as a new bit. -- -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) ------------------------------------------------------------------------------ function bcd_to_slv_pipe( BCD_RVal : std_logic_vector; -- registered output of this function fed back in BCD_DigitsVal : integer) return std_logic_vector is -- binary coded decimal arithmetic shift right variable BCDVar : std_logic_vector(BCD_RVal'length-1 downto 0); variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0) := (others => '0'); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); variable BCD_WiCarVar : std_logic_vector(3 downto 0); variable ResultVar : std_logic_vector(4*BCD_DigitsVal-1 downto 0); begin BCDVar := BCD_RVal; CarryVar(CarryVar'high) := '0'; for loopVar in BCD_DigitsVal-1 downto 0 loop BCD_WoCarVar := '0' & BCDVar(4*loopVar+3 downto 4*loopVar+1); BCD_WiCarVar := BCD_WoCarVar + "0101"; CarryVar(loopVar) := BCDVar(4*loopVar); if (CarryVar(loopVar+1) = '1') then ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WiCarVar; else ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WoCarVar; end if; end loop; return ResultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : bv_to_slv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an bit vector -- to a std logic vector. -- -- NOTES -- ------------------------------------------------------------------------------ function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector is begin return To_StdLogicVector(bitVectVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cdft (count down for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value (minus 2 for -- latency for counting down to an underflow for) using -- a string based frequency value, as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a variable -- value (CountValIn) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig(CountRSig'high) = '1') then -- CountSig <= CountValIn; -- PulseSig <= '1'; -- else -- CountSig <= CountRSig - 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cdft(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce((timeVar/freqStrVar) - 2); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cdft (count down for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value (minus 2 for -- latency for counting down to an underflow for) using -- a string based frequency (or period) value as a time -- base reference and a natural value for -- the length of the vector to return -- (if it will fit in a vector that size) -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a variable -- value (CountValIn) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig(CountRSig'high) = '1') then -- CountSig <= CountValIn; -- PulseSig <= '1'; -- else -- CountSig <= CountRSig - 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cdft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable lengthVar : natural; variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable zeroVar : std_logic_vector(natVal - cdfth(timeStrVal,freqStrVal) - 2 downto 0) := (others => '0'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); lengthVar := reduce_length((timeVar/freqStrVar) - 2); if (lengthVar >= natVal) then return reduce((timeVar/freqStrVar) - 2); else return zeroVar & reduce((timeVar/freqStrVar) - 2); end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cdfth (count down for time high) -- -- DESCRIPTION : This function computes the vector'high value -- from a string based time value (minus a count of 2 -- for use in counting down to underflow) and -- converts it to a std_logic_vector value using -- the a string based period value, as a reference -- This function requires units in each string -- -- NOTES -- ------------------------------------------------------------------------------ function cdfth(timeStrVal : string; freqStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_high((timeVar/freqStrVar) - 2); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : ceil -- -- DESCRIPTION : This function rounds a real value up to the next -- real integer -- -- NOTES -- ------------------------------------------------------------------------------ function ceil (RealVal : in real) return real is constant integerMaxVal : real := real(integer'high); variable RoundVar : real; variable ResultVar : real; begin RoundVar := real(integer(RealVal)); if (abs(RealVal) >= integerMaxVal) then ResultVar := RealVal; elsif (RoundVar = RealVal) then ResultVar := RoundVar; elsif (RealVal > 0.0) then if (RoundVar >= RealVal) then ResultVar := RoundVar; else ResultVar := RoundVar + 1.0; end if; elsif (RealVal = 0.0) then ResultVar := 0.0; else if (RoundVar <= RealVal) then ResultVar := RoundVar + 1.0; else ResultVar := RoundVar; end if; end if; return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cfi (characters for integer) -- -- DESCRIPTION : This function returns a natural representing the -- number of characters required to reprsent an -- integer value. It is essentially -- an integer'length function for the characters. -- -- NOTES : -- ------------------------------------------------------------------------------ function cfi(intVal : integer) return natural is variable intVar : integer; variable negVar : boolean; begin if (intVal < 0) then intVar := -intVal; negVar := true; else intVar := intVal; negVar := false; end if; for LoopVar in 1 to MAX_VECT_SIZE loop if (intVar = 0) then return 1; elsif (intVar < 10 and intVar >= 1) then if (negVar) then return loopVar + 1; -- allow for the '-' character else return loopVar; end if; else intVar := intVar/10; end if; end loop; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cft (count for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference. -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cft(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce(timeVar/freqStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cft (count for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency (or period) value as a time -- base reference and a natural value for -- the length of the vector to return -- (if it will fit in a vector that size) -- This function requires units in each string -- -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable lengthVar : natural; variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable zeroVar : std_logic_vector(natVal - cfth(timeStrVal,freqStrVal) - 2 downto 0) := (others => '0'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); lengthVar := reduce_length(timeVar/freqStrVar); if (lengthVar >= natVal) then return reduce(timeVar/freqStrVar); else return zeroVar & reduce(timeVar/freqStrVar); end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cfth (count for time high) -- -- DESCRIPTION : This function computes the vector'high value -- from a string based time value using -- the a string based frequency (or period) -- value, as a reference -- This function requires units in each string -- -- NOTES -- ------------------------------------------------------------------------------ function cfth(timeStrVal : string; freqStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_high(timeVar/freqStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cftu (count for time unsigned) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cftu(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_unsigned(timeVar/freqStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cftu (count for time unsigned) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function cftu(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable fudgeStrVar : integer; begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); fudgeStrVar := str_to_int(fudgeStrVal); return reduce_unsigned(timeVar/freqStrVar + fudgeStrVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : clkcnt (50% duty cycle clock count) -- -- DESCRIPTION : This function takes a string based frequency value and -- converts it to a std_logic_vector value using -- a string based frequency value, as a reference -- NOTES -- this function is for use with a process which counts -- up to a static value. This method tends to give the smallest and -- fastest circuit -- --CounterProcess2 rocess(ClkRSig,Count2RSig)-- variable CLKCNTVAL : std_logic_vector := clkcnt("Freq1StrVal","Freq2StrVal") --begin -- if (Count2RSig = CLKCNTVAL) then -- Count2Sig <= (others => '0'); -- ClkSig <= not ClkRSig; -- else -- Count2Sig <= Count2RSig + 1; -- ClkSig <= ClkRSig; -- end if; --end process; -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. ------------------------------------------------------------------------------ function clkcnt(freq1StrVal : string; freq2StrVal : string) return std_logic_vector is variable freq1StrVar : std_logic_vector(strval_to_slv_var_base_high(freq1 StrVal,CFT_BASE_SIZE) downto 0); variable freq2StrVar : std_logic_vector(strval_to_slv_var_base_high(freq2 StrVal,CFT_BASE_SIZE) downto 0); begin freq1StrVar := strval_to_slv(freq1StrVal,CFT_BASE_SIZE); freq2StrVar := strval_to_slv(freq2StrVal,CFT_BASE_SIZE); return reduce_unsigned((freq1StrVar/freq2StrVar)/2-1); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : conv_to_hex -- -- DESCRIPTION : This function converts a bit vector of any length to a -- string representing the Hexadecimal value of that vector -- NOTES -- ------------------------------------------------------------------------------ function conv_to_hex(vectorVal : bit_vector) return string is variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1); variable vectorParseVar : std_logic_vector(4 downto 1); variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'leng th)/4.0)))*4 downto 1); variable VectorVar : bit_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; vectorStretchVar := ext(to_stdlogicvector(VectorVar),vectorStretchVar' length); for loopVar in resultVar'range loop vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-3); case vectorParseVar(4 downto 1) is when x"0" => resultVar(loopVar) := '0'; when x"1" => resultVar(loopVar) := '1'; when x"2" => resultVar(loopVar) := '2'; when x"3" => resultVar(loopVar) := '3'; when x"4" => resultVar(loopVar) := '4'; when x"5" => resultVar(loopVar) := '5'; when x"6" => resultVar(loopVar) := '6'; when x"7" => resultVar(loopVar) := '7'; when x"8" => resultVar(loopVar) := '8'; when x"9" => resultVar(loopVar) := '9'; when x"A" => resultVar(loopVar) := 'A'; when x"B" => resultVar(loopVar) := 'B'; when x"C" => resultVar(loopVar) := 'C'; when x"D" => resultVar(loopVar) := 'D'; when x"E" => resultVar(loopVar) := 'E'; when x"F" => resultVar(loopVar) := 'F'; when others => end case; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : conv_to_hex -- -- DESCRIPTION : This function converts a logic vector of any length to a -- string representing the Hexadecimal value of that vector -- NOTES -- ------------------------------------------------------------------------------ function conv_to_hex(vectorVal : std_logic_vector) return string is variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1); variable vectorParseVar : std_logic_vector(4 downto 1); variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'leng th)/4.0)))*4 downto 1); variable VectorVar : std_logic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; vectorStretchVar := ext(VectorVar,vectorStretchVar'length); for loopVar in resultVar'range loop vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-3); case vectorParseVar(4 downto 1) is when x"0" => resultVar(loopVar) := '0'; when x"1" => resultVar(loopVar) := '1'; when x"2" => resultVar(loopVar) := '2'; when x"3" => resultVar(loopVar) := '3'; when x"4" => resultVar(loopVar) := '4'; when x"5" => resultVar(loopVar) := '5'; when x"6" => resultVar(loopVar) := '6'; when x"7" => resultVar(loopVar) := '7'; when x"8" => resultVar(loopVar) := '8'; when x"9" => resultVar(loopVar) := '9'; when x"A" => resultVar(loopVar) := 'A'; when x"B" => resultVar(loopVar) := 'B'; when x"C" => resultVar(loopVar) := 'C'; when x"D" => resultVar(loopVar) := 'D'; when x"E" => resultVar(loopVar) := 'E'; when x"F" => resultVar(loopVar) := 'F'; when others => end case; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : conv_to_hex -- -- DESCRIPTION : This function converts a ulogic vector of any length to a -- string representing the Hexadecimal value of that vector -- NOTES -- ------------------------------------------------------------------------------ function conv_to_hex(vectorVal : std_ulogic_vector) return string is variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1); variable vectorParseVar : std_logic_vector(4 downto 1); variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'leng th)/4.0)))*4 downto 1); variable VectorVar : std_ulogic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; vectorStretchVar := ext(to_stdlogicvector(VectorVar),vectorStretchVar' length); for loopVar in resultVar'range loop vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-3); case vectorParseVar(4 downto 1) is when x"0" => resultVar(loopVar) := '0'; when x"1" => resultVar(loopVar) := '1'; when x"2" => resultVar(loopVar) := '2'; when x"3" => resultVar(loopVar) := '3'; when x"4" => resultVar(loopVar) := '4'; when x"5" => resultVar(loopVar) := '5'; when x"6" => resultVar(loopVar) := '6'; when x"7" => resultVar(loopVar) := '7'; when x"8" => resultVar(loopVar) := '8'; when x"9" => resultVar(loopVar) := '9'; when x"A" => resultVar(loopVar) := 'A'; when x"B" => resultVar(loopVar) := 'B'; when x"C" => resultVar(loopVar) := 'C'; when x"D" => resultVar(loopVar) := 'D'; when x"E" => resultVar(loopVar) := 'E'; when x"F" => resultVar(loopVar) := 'F'; when others => end case; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : crc16 -- -- DESCRIPTION : returns the input to a Cyclic Redundancy Check (CRC) -- using the polynomial x^16 + x^15 + x^2 + 1 -- (CRC-16-CCITT) -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- -- http://en.wikipedia.org/wiki/LFSR ------------------------------------------------------------------------------ function crc16(serialInVal : std_logic; vectorVal : std_logic_vector) return std_logic_vector is -- constant OUTPUT_FILE : string := LOG_PATH & "crc16_function_logfile" & LOG_EXT; -- variable LogFileLine : line; -- file LogFile : text open write_mode is OUTPUT_FILE; variable vector1Var : std_logic_vector(1 to 16); -- CRCs are usually depicted shifting left to right with the right being the MSB variable vector2Var : std_logic_vector(1 to 16); -- CRCs are usually depicted shifting left to right with the right being the MSB begin vector1Var := vectorVal; vector2Var := '0' & vector1Var(1 to 15); -- default to vector1Var shifted right vector2var(1) := serialInVal xor vector1Var(15); vector2Var(3) := serialInVal xor vector1Var(2) xor vector1Var(16); vector2Var(16) := serialInVal xor vector1Var(15) xor vector1Var(16); return vector2Var; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cslv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an integer (int1Val) -- to a std logic vector of length int2Val. -- -- NOTES -- ------------------------------------------------------------------------------ function cslv(int1Val : integer; int2Val : integer) return std_logic_vector is begin return conv_std_logic_vector(int1Val,int2Val); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cslv (convert signed to std_logic_vector) -- -- DESCRIPTION : This function converts an signed value -- to a std logic vector of length intVal. -- -- NOTES -- ------------------------------------------------------------------------------ function cslv(sigVal : signed; intVal : integer) return std_logic_vector is begin return conv_std_logic_vector(sigVal,intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cslv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an unsigned value -- to a std logic vector of length intVal. -- -- NOTES -- ------------------------------------------------------------------------------ function cslv(usgVal : unsigned; intVal : integer) return std_logic_vector is begin return conv_std_logic_vector(usgVal,intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cuft (count up for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector (minus one for latency) -- value using a string based frequency (or period) value, -- as a reference -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to. -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a constant -- value (COUNTVALUE) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig = COUNTVALUE) then -- CountSig <= (others => '0'); -- PulseSig <= '1'; -- else -- CountSig <= CountRSig + 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cuft(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_unsigned((timeVar/freqStrVar) - 1); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cuft (count up for time) -- -- DESCRIPTION : This function takes a string based time value and -- converts it to a std_logic_vector (minus one for latency) -- value using a string based frequency (or period) value -- as a time base reference and a natural value for -- the length of the vector to return -- (if it will fit in a vector that size) -- This function requires units in each string -- -- NOTES -- -- if the following error occurs it is due to an improperly sized vector -- that the result of this function is assigned to: -- --# ** Fatal: (vsim-3420) Array lengths do not match. -- -- This function is best used to determine a constant -- value (COUNTVALUE) for use with a counter styled similarly -- to this: -- -- CounterProcess rocess(CountRSig,CountValIn)-- begin -- if (CountRSig = COUNTVALUE) then -- CountSig <= (others => '0'); -- PulseSig <= '1'; -- else -- CountSig <= CountRSig + 1; -- PulseSig <= '0'; -- end if; -- end process; -- ------------------------------------------------------------------------------ function cuft(timeStrVal : string; freqStrVal : string; natVal : natural) return std_logic_vector is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable lengthVar : natural; variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); variable zeroVar : std_logic_vector(natVal - cufth(timeStrVal,freqStrVal) - 2 downto 0) := (others => '0'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); lengthVar := reduce_length_unsigned((timeVar/freqStrVar) - 1); if (lengthVar >= natVal) then return reduce_unsigned((timeVar/freqStrVar) - 1); else return zeroVar & reduce_unsigned((timeVar/freqStrVar) - 1); end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : cufth (count up for time high) -- -- DESCRIPTION : This function computes the vector'high value -- from a string based time value (minus a count of 1 -- for use in counting up from zero to the proper value) using -- the a string based period value, as a reference -- This function requires units in each string -- -- NOTES -- ------------------------------------------------------------------------------ function cufth(timeStrVal : string; freqStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0); variable timeVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); return reduce_high_unsigned((timeVar/freqStrVar) - 1); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfi (decimal places for integer) -- -- DESCRIPTION : This function returns a natural representing the -- number of digits in an integer value. It is essentially -- an integer'length function (does not count -- a '-' character). -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfi(intVal : integer) return natural is variable intVar : integer; variable CountVar : natural := 1; variable ResultVar : natural; begin if (intVal < 0) then intVar := -intVal; else intVar := intVal; end if; for CountVar in 1 to MAX_VECT_SIZE loop if (intVal = 0) then return 1; elsif (intVar < 10 and intVar >= 1) then return CountVar; else intVar := intVar/10; end if; end loop; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfi_syn (decimal places for integer (synthesizeable)) -- -- DESCRIPTION : This function returns a natural representing the -- number of digits in an integer value. It is essentially -- an integer'length function. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfi_syn(intVal : integer) return natural is variable resultVar : natural; begin if (intVal <= -1_000_000_000 or intVal >= 1_000_000_000) then resultVar := 10; elsif (intVal <= -100_000_000 or intVal >= 100_000_000) then resultVar := 9; elsif (intVal <= -10_000_000 or intVal >= 10_000_000) then resultVar := 8; elsif (intVal <= -1_000_000 or intVal >= 1_000_000) then resultVar := 7; elsif (intVal <= -100_000 or intVal >= 100_000) then resultVar := 6; elsif (intVal <= -10_000 or intVal >= 10_000) then resultVar := 5; elsif (intVal <= -1_000 or intVal >= 1_000) then resultVar := 4; elsif (intVal <= -100 or intVal >= 100) then resultVar := 3; elsif (intVal <= -10 or intVal >= 10) then resultVar := 2; else resultVar := 1; end if; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfr (decimal places for real) -- -- DESCRIPTION : This function returns a natural value representing the -- number of digits to the left of the decimal -- in a real value. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfr(realVal : real) return natural is variable realVar : real; variable ResultVar : natural; begin if (realVal < 0.0) then realVar := -realVal; else realVar := realVal; end if; for loopVar in 1 to MAX_VECT_SIZE loop if (realVal = 0.0) then return 1; elsif (realVar < 10.0 and realVar >= 1.0) then return loopVar; else realVar := realVar/10.0; end if; end loop; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfslvr (decimal places for slv range) -- -- DESCRIPTION : This function returns a natural representing the -- number of decimal places the largest integer value that -- can be represented by a vector will occupy. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfslvr(vectorVal : std_logic_vector) return natural is variable returnVar : std_logic_vector(vectorVal'length-1 downto 0) := (others => '1'); begin return dpfi(conv_integer(returnVar)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : dpfslvv (decimal places for slv value) -- -- DESCRIPTION : This function returns a natural representing the -- number of decimal places the integer value represented -- by a vector will occupy. -- -- NOTES : -- ------------------------------------------------------------------------------ function dpfslvv(vectorVal : std_logic_vector) return natural is begin return dpfi(conv_integer(vectorVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : eq -- -- DESCRIPTION : This function is an equality check function -- that is sensitive to vector length -- NOTES -- ------------------------------------------------------------------------------ function eq(vector1Val : std_logic_vector; vector2Val : std_logic_vector) return boolean is variable sl1Var : std_logic; variable sl2Var : std_logic; variable resultVar : boolean; variable vector1Var : std_logic_vector(vector1Val'length-1 downto 0); variable vector2Var : std_logic_vector(vector2Val'length-1 downto 0); begin resultVar := true; vector1Var := vector1Val; vector2Var := vector2Val; if (vector1Var'high /= vector2Var'high) then -- check for length mismatch return false; end if; for loopVar in vector1Var'range loop if (vector1Var(loopVar) /= vector2Var(loopVar)) then resultVar := false; end if; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : ext (space extend) -- -- DESCRIPTION : This function returns a string, -- padded with spaces, to the length specified by natVal -- -- NOTES : -- ------------------------------------------------------------------------------ function ext(strVal : string; natVal : natural) return string is variable resultVar : string(1 to natVal); variable strVar : string(1 to strVal'length); variable spaceVar : string(1 to max(natVal-strVal'length,1)); begin strVar := strVal; if (strVal'length >= natVal) then return strVal; else for loopVar in spaceVar'range loop spaceVar(loopVar) := ' '; -- fill with spaces end loop; end if; resultVar := spaceVar & strVar; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : ext2 (zero extend) -- -- DESCRIPTION : This function returns a standard logic vector, -- padded with zeros, to the length specified by natVal -- -- NOTES : -- ------------------------------------------------------------------------------ function ext2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector is variable vectorVar : std_logic_vector (vectorVal'length - 1 downto 0); variable zeroVar : std_logic_vector (natVal - vectorVal'length - 1 downto 0) := (others => '0'); begin vectorVar := vectorVal; if (vectorVar'length >= natVal) then return vectorVar; else return zeroVar & vectorVar; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : flip -- -- DESCRIPTION : This function returns a vector with all the bits -- in the vector flipped. -- i.e. if vectorval = 00011001 -- flip(vectorval) returns 10011000 -- NOTES -- ------------------------------------------------------------------------------ function flip(vectorVal : bit_vector) return bit_vector is variable resultVar : bit_vector(vectorVal'range); begin for loopVar in vectorVal'range loop resultVar(resultVar'high-loopVar) := vectorVal(loopVar); end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : flip -- -- DESCRIPTION : This function returns a vector with all the bits -- in the vector flipped. -- i.e. if vectorval = 00011001 -- flip(vectorval) returns 10011000 -- NOTES -- ------------------------------------------------------------------------------ function flip(vectorVal : std_logic_vector) return std_logic_vector is variable resultVar : std_logic_vector(vectorVal'range); begin for loopVar in vectorVal'range loop resultVar(resultVar'high-loopVar) := vectorVal(loopVar); end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : flip -- -- DESCRIPTION : This function returns a vector with all the bits -- in the vector flipped. -- i.e. if vectorval = 00011001 -- flip(vectorval) returns 10011000 -- NOTES -- ------------------------------------------------------------------------------ function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector is variable resultVar : std_ulogic_vector(vectorVal'range); begin for loopVar in vectorVal'range loop resultVar(resultVar'high-loopVar) := vectorVal(loopVar); end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : floor -- -- DESCRIPTION : This function rounds a real value down to the next -- real integer -- -- NOTES -- ------------------------------------------------------------------------------ function floor(RealVal : in real) return real is constant integerMaxVal : real := real(integer'high); variable RoundVar : real; variable ResultVar : real; begin RoundVar := real(integer(RealVal)); -- eliminate all the digits after the decimal point if (abs(RealVal) >= integerMaxVal) then -- if the real value is larger than the maximum integer value then we can't continue ResultVar := RealVal; elsif (RoundVar = RealVal) then -- if it's equal then return the same value ResultVar := RoundVar; elsif (RealVal > 0.0) then -- if its greater then 0.0 it's positve so we return the less postive number if (RoundVar >= RealVal) then ResultVar := RoundVar - 1.0; else ResultVar := RoundVar; end if; elsif (RealVal = 0.0) then -- if it's 0.0 then return 0.0 ResultVar := 0.0; else if (RoundVar <= RealVal) then -- if its less then 0.0 it's negative so we return the more negative number ResultVar := RoundVar; else ResultVar := RoundVar - 1.0; end if; end if; return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : hex_to_slv -- -- DESCRIPTION : This function converts a Hexadecimal value string -- of any length to a std_logic_vector -- -- NOTES -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function hex_to_slv(stringVal : string) return std_logic_vector is variable stringVar : string(1 to stringVal'length); variable resultVar : std_logic_vector(4*stringVal'length downto 1); variable vectorParseVar : character; begin stringVar := stringVal; for loopVar in stringVar'range loop vectorParseVar := stringVar(loopVar); case vectorParseVar is when '0' => resultVar(4*loopVar downto 4*loopvar-3) := x"0"; when '1' => resultVar(4*loopVar downto 4*loopvar-3) := x"1"; when '2' => resultVar(4*loopVar downto 4*loopvar-3) := x"2"; when '3' => resultVar(4*loopVar downto 4*loopvar-3) := x"3"; when '4' => resultVar(4*loopVar downto 4*loopvar-3) := x"4"; when '5' => resultVar(4*loopVar downto 4*loopvar-3) := x"5"; when '6' => resultVar(4*loopVar downto 4*loopvar-3) := x"6"; when '7' => resultVar(4*loopVar downto 4*loopvar-3) := x"7"; when '8' => resultVar(4*loopVar downto 4*loopvar-3) := x"8"; when '9' => resultVar(4*loopVar downto 4*loopvar-3) := x"9"; when 'a' | 'A' => resultVar(4*loopVar downto 4*loopvar-3) := x"A"; when 'b' | 'B' => resultVar(4*loopVar downto 4*loopvar-3) := x"B"; when 'c' | 'C' => resultVar(4*loopVar downto 4*loopvar-3) := x"C"; when 'd' | 'D' => resultVar(4*loopVar downto 4*loopvar-3) := x"D"; when 'e' | 'E' => resultVar(4*loopVar downto 4*loopvar-3) := x"E"; when 'f' | 'F' => resultVar(4*loopVar downto 4*loopvar-3) := x"F"; when others => end case; end loop; return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : int_to_slv (convert integer to std_logic_vector) -- -- DESCRIPTION : This function converts an integer value to a -- std_logic_vector with a range just large enough -- to represent it -- -- NOTES -- ------------------------------------------------------------------------------ function int_to_slv(intVal : integer) return std_logic_vector is begin return conv_std_logic_vector(intVal,vlfi(intVal)); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : itoa -- -- DESCRIPTION : commonly used integer-to-string type converter -- -- NOTES -- ------------------------------------------------------------------------------ --function itoa(intVal : integer) return string is -- variable IntVar : integer := intVal; --begin -- if (IntVar < 0) then -- return "-" & itoa(-IntVar); -- elsif IntVar < 10 then -- return IntString(IntVar); -- else -- return itoa(IntVar/10) & IntString(IntVar rem 10); -- end if; --end function itoa; function itoa(intVal : integer) return string is begin return to_string(intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr (Linear Feedback Shift Register) -- -- DESCRIPTION : returns the input for the next cycle of a -- Linear Feedback Shift Register (LFSR) -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- ------------------------------------------------------------------------------ function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string; polynomialStrVal : string) return std_logic_vector is type termArrayType is array (1 to 20) of integer; -- supports up to 20 terms in a polynomial constant polynomialConst : string := polynomialStrVal; -- holds the string containing the exponent values (from highest to lowest power, separated by commas or + signs) variable seperatorLocationVar : integer; -- marks the location of the last exponent seperator variable polynomialParseVar : character; -- character value used to index through the polynomialVar string to look for seperators variable tapFoundVar : boolean; variable termArray : termArrayType; variable termQtyVar : integer; -- used to determine the number of terms in the polynomial variable type2Var : boolean; variable typeParseVar : character; variable typeVar : string(1 to lfsrTypeVal'length); variable typeXORVar : boolean; variable vector1Var : std_logic_vector(1 to vectorVal'length); -- LFSRs are usually depicted shifting left to right with the right being the MSB variable vector2Var : std_logic_vector(1 to vectorVal'length); -- LFSRs are usually depicted shifting left to right with the right being the MSB begin seperatorLocationVar := 1; tapFoundVar := FALSE; for loopVar in termArray'range loop termArray(loopVar) := 0; -- initialize to 0s end loop; termQtyVar := 1; type2Var := TRUE; typeVar := lfsrTypeVal; typeXORVar := TRUE; vector1Var := vectorVal; vector2Var := vector1Var; polynomial_string_parser : for loopVar in polynomialConst'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found polynomialParseVar := polynomialConst(loopVar); if (polynomialParseVar = ',' or polynomialParseVar = '+') then termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; termQtyVar := termQtyVar + 1; elsif (loopVar = polynomialConst'high) then -- this is the last term termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; end if; end loop polynomial_string_parser; type_string_parser : for loopVar in typeVar'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found typeParseVar := typeVar(loopVar); if (typeParseVar = 'n' or typeParseVar = 'N') then -- if there is an n or N present it must be an XNOR type feedback typeXORVar := FALSE; elsif (typeParseVar = '1') then -- if there is an 1 present it must be type 1 feedback type2Var := FALSE; end if; end loop type_string_parser; if (not type2Var) then -- Type 1 feedback (Fibonacci) (many output to one input) if (not typeXORVar) then vector2Var(vector2Var'low) := '1'; for loopVar in 1 to termQtyVar loop -- this loop determines the next input value for a Type 1 LFSR vector2Var(vector2Var'low) := not (vector1Var(termArray(loopVar)) xor vector2Var(vector2Var'low)); end loop; vector2Var := vector2Var(vector2Var'low) & vector1Var(vector1Var'low to vector1Var'high-1); else vector2Var(vector2Var'low) := '0'; for loopVar in 1 to termQtyVar loop -- this loop determines the next input value for a Type 1 LFSR vector2Var(vector2Var'low) := vector1Var(termArray(loopVar)) xor vector2Var(vector2Var'low); end loop; vector2Var := vector2Var(vector2Var'low) & vector1Var(vector1Var'low to vector1Var'high-1); end if; else -- Type 2 feedback (Galois) (one output to many inputs) if (not typeXORVar) then vector2var(vector2var'low) := vector1Var(vector1Var'high); -- highest power term alway wraps around to the input for outrLoopVar in 2 to vector2Var'high loop -- this loop determines the next value for the LFSR tapFoundVar := FALSE; for innrLoopVar in 2 to termQtyVar loop -- highest power term (termArray(1)) isn't needed below if (termArray(innrLoopVar) = outrLoopVar-1) then tapFoundVar := TRUE; vector2Var(outrLoopVar) := not (vector1Var(outrLoopVar-1) xor vector1Var(vector1Var'high)); -- xor in where a tap should be elsif (not tapFoundVar) then vector2Var(outrLoopVar) := vector1Var(outrLoopVar-1); -- if there's no tap then get the previous registers value end if; end loop; end loop; else vector2var(vector2var'low) := vector1Var(vector1Var'high); -- highest power term alway wraps around to the input for outrLoopVar in 2 to vector2Var'high loop -- this loop determines the next value for the LFSR tapFoundVar := FALSE; for innrLoopVar in 2 to termQtyVar loop -- highest power term (termArray(1)) isn't needed below if (termArray(innrLoopVar) = outrLoopVar-1) then tapFoundVar := TRUE; vector2Var(outrLoopVar) := vector1Var(outrLoopVar-1) xor vector1Var(vector1Var'high); -- xor in where a tap should be elsif (not tapFoundVar) then vector2Var(outrLoopVar) := vector1Var(outrLoopVar-1); -- if there's no tap then get the previous registers value end if; end loop; end loop; end if; end if; return vector2Var; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr -- -- DESCRIPTION : returns the input for the next cycle of a -- Linear Feedback Shift Register (LFSR) -- using a primitive polynomial -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- ------------------------------------------------------------------------------ function lfsr(vectorVal : std_logic_vector; lfsrTypeVal : string) return std_logic_vector is begin return lfsr(vectorVal,lfsrTypeVal,LFSR_Polynomial_Exponen ts(vectorVal'length)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr -- -- DESCRIPTION : returns the input for the next cycle of a -- Linear Feedback Shift Register (LFSR) -- using a primitive polynomial. This version uses -- a Type 2 XOR feedback structure -- -- NOTES: the output from this function is clocked into the input -- registers of the LFSR. The LFSR is shifted -- to the right, MSB to LSB, with each clock. The LFSR -- must be pre-loaded with a non zero seed value to function. -- ------------------------------------------------------------------------------ function lfsr(vectorVal : std_logic_vector) return std_logic_vector is begin return lfsr(vectorVal,"Type 2 xor",LFSR_Polynomial_Exponents(vectorVal'length)) ; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft -- -- DESCRIPTION : returns the value a Linear Feedback Shift Register -- (LFSR) will contain after the amount -- of time specified using the frequency (or period) -- value passed as a reference and the seed value -- passed as a starting point -- -- NOTES : this function will probably run slowly when used for synthesis -- ------------------------------------------------------------------------------ function lfsr_cft(timeStrVal : string; freqStrVal : string; seedVal : std_logic_vector; lfsrTypeVal : string; fudgeStrVal : string) return std_logic_vector is -- synopsys translate_off constant OUTPUT_FILE : string := LOG_PATH & "lfsr_cft_function_logfile" & LOG_EXT; variable LogFileLine : line; file LogFile : text; --open append_mode is OUTPUT_FILE; -- synopsys translate_on type termArrayType is array (1 to 20) of integer; -- supports up to 20 terms in a polynomial constant high : integer := lfsr_cfth(timeStrVal,freqStrVal,fudgeStrVal); constant length : integer := high+1; constant lowerBound : integer := LFSRLowerBound; constant upperBound : integer := LFSRUpperBound; constant polynomialConst : string := LFSR_Polynomial_Exponents(length); -- holds the string containing the exponent values (from highest to lowest power, separated by commas or + signs) variable countDoneVar : std_logic_vector(high downto 0) := ext(cftu(timeStrVal,freqStrVal,fudgeStrVal),length ); -- stop value for counter used to determine when the loop which computes the lfsr stop value should stop looping variable countVar : std_logic_vector(high downto 0) := (others => '0'); -- counter counter used to determine when the loop which computes the lfsr stop value should stop looping variable fudgeVar : string(1 to fudgeStrVal'length) := fudgeStrVal; -- shift the count by the number indicated variable lfsr_strIndexVar : integer := 0; variable loopEnableVar : boolean := TRUE; variable polynomialParseVar : character; -- character value used to index through the polynomialVar string to look for seperators variable seedVar : std_logic_vector(high downto 0) := ext(seedVal,length); variable seperatorLocationVar : integer := 1; -- marks the location of the last exponent seperator variable stopVar : std_logic_vector(high downto 0) := (others => '1'); variable tapFoundVar : boolean := FALSE; variable termArray : termArrayType; variable termQtyVar : integer := 1; -- used to determine the number of terms in the polynomial variable type2FBVar : boolean := TRUE; variable typeParseVar : character; variable typeSimLoopVar : boolean := TRUE; variable typeVar : string(1 to lfsrTypeVal'length) := lfsrTypeVal; variable typeXORVar : boolean := TRUE; variable vector1Var : std_logic_vector(1 to length) := seedVar; -- LFSRs are usually depicted shifting left to right with the right being the MSB variable vector2Var : std_logic_vector(1 to length) := seedVar; -- LFSRs are usually depicted shifting left to right with the right being the MSB variable xorMaskVar : std_logic_vector(1 to length) := (others => '0'); -- holds the xor feedback variable begin -- synopsys translate_off file_open(LogFile, OUTPUT_FILE, append_mode); -- synopsys translate_on for loopVar in lowerBound to length-1 loop lfsr_strIndexVar := 2**loopVar-1 + lfsr_strIndexVar; end loop; lfsr_strIndexVar := lfsr_strIndexVar + to_int(countDoneVar) + 1; array_initializer : for loopVar in termArray'range loop termArray(loopVar) := 0; -- initialize to 0s end loop array_initializer; polynomial_string_parser : for loopVar in polynomialConst'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found polynomialParseVar := polynomialConst(loopVar); if (polynomialParseVar = ',' or polynomialParseVar = '+') then -- commas or '+' signs can be used as seperators for the exponents termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; termQtyVar := termQtyVar + 1; elsif (loopVar = polynomialConst'high) then -- this is the last term termArray(termQtyVar) := str_to_int(polynomialConst(seperatorLocationVar to loopVar)); seperatorLocationVar := loopVar; end if; end loop polynomial_string_parser; xor_vector_computer : for outrLoopVar in xorMaskVar'range loop -- compute the value that the xor vector should have to make an LFSR with a given polynomial for innrLoopVar in 1 to termQtyVar loop if (termArray(innrLoopVar) = outrLoopVar) then xorMaskVar(outrLoopVar) := '1'; end if; end loop; end loop xor_vector_computer; type_string_parser : for loopVar in typeVar'range loop -- this loop parses the polynomial string value passed from the Polynomial array from left to right and puts each exponent in the termArray and counts the number of exponents found typeParseVar := typeVar(loopVar); if (typeParseVar = 'n' or typeParseVar = 'N') then -- if there is an n or N present it must be an XNOR type feedback typeXORVar := FALSE; elsif (typeParseVar = '1') then -- if there is an 1 present it must be type 1 feedback type2FBVar := FALSE; elsif (typeParseVar = 's' or typeParseVar = 'S') then if (typeVar(loopVar+1) = 'y' or typeVar(loopVar+1) = 'Y') then typeSimLoopVar := FALSE; -- this function call must be for synthesis end if; end if; end loop type_string_parser; if typeSimLoopVar then if (not type2FBVar) then -- Type 1 feedback (Fibonacci) (many output to one input) if (not typeXORVar) then type1_xnor_stop_value_computer : while loopEnableVar loop if loopEnableVar then countVar := countVar + 1; vector2Var := xnor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type1_xnor_stop_value_computer; else type1_xor_stop_value_computer : while loopEnableVar loop if loopEnableVar then countVar := countVar + 1; vector2Var := xor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type1_xor_stop_value_computer; end if; else -- Type 2 feedback (Galois) (one output to many inputs) if (not typeXORVar) then xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); type2_xnor_stop_value_computer : while loopEnableVar loop if (vector1Var(vector1Var'high) = '1' and loopEnableVar) then countVar := countVar + 1; vector2Var := not ((vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor not(xorMaskVar)); -- shift right and apply xnor vector1Var := vector2Var; elsif (loopEnableVar) then countVar := countVar + 1; vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type2_xnor_stop_value_computer; else xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); type2_xor_stop_value_computer : while loopEnableVar loop if (vector1Var(vector1Var'high) = '1' and loopEnableVar) then countVar := countVar + 1; vector2Var := (vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor xorMaskVar; -- shift right and apply xor vector1Var := vector2Var; elsif (loopEnableVar) then countVar := countVar + 1; vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; if (countVar = countDoneVar) then loopEnableVar := FALSE; end if; end loop type2_xor_stop_value_computer; end if; end if; else -- synthesis oriented version below (no while loops that the synthesis tool struggles with) if (not type2FBVar) then -- Type 1 feedback (Fibonacci) (many output to one input) if (not typeXORVar) then syn_type1_xnor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop vector2Var := xnor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end loop syn_type1_xnor_stop_value_computer; else syn_type1_xor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop vector2Var := xor_reduce(vector1Var and xorMaskvar) & vector1Var(1 to vector1Var'high-1); -- shift right and apply xnor vector1Var := vector2Var; end loop syn_type1_xor_stop_value_computer; end if; else -- Type 2 feedback (Galois) (one output to many inputs) if (not typeXORVar) then xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); syn_type2_xnor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop if (vector1Var(vector1Var'high) = '1') then vector2Var := not ((vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor not(xorMaskVar)); -- shift right and apply xnor vector1Var := vector2Var; else vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; end loop syn_type2_xnor_stop_value_computer; else --vector2Var := str_to_slv(lfsr_str(lfsr_strIndexVar)); xorMaskVar := '0' & xorMaskVar(1 to xorMaskVar'high-1); syn_type2_xor_stop_value_computer : for loopVar in 0 to to_int(countDoneVar) loop if (vector1Var(vector1Var'high) = '1') then vector2Var := (vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1)) xor not(xorMaskVar); -- shift right and apply xor vector1Var := vector2Var; else vector2Var := vector1Var(vector1Var'high) & vector1Var(1 to vector1Var'high-1); vector1Var := vector2Var; end if; end loop syn_type2_xor_stop_value_computer; end if; end if; end if; stopVar := vector2Var; -- synopsys translate_off write(LogFileLine, LF & "polynomialConst : " & to_string(lfsr_cfth(timeStrVal,freqStrVal,fudgeStr Val)+1) & LF & "exponent values : " & polynomialConst & LF & "xorMaskVar value : " & to_string(xorMaskVar) & LF & "LFSR count time : " & timeStrVal & LF & "reference time/period : " & freqStrVal & LF & "fudge factor : " & fudgeStrVal & LF & "type2FBVar : " & to_string(type2FBVar) & LF & "typeXORVar : " & to_string(typeXORVar) & LF & "# of clock cycles : " & to_string(to_int(countDoneVar)) & LF & "LFSR length : " & to_string(stopVar'length) & LF & "LFSR stop value : " & to_string(stopVar) & LF & LF ); writeLine(LogFile,LogFileLine); assert FALSE report LF & "polynomialConst : " & to_string(lfsr_cfth(timeStrVal,freqStrVal,fudgeStr Val)+1) & LF & "exponent values : " & polynomialConst & LF & "xorMaskVar value : " & to_string(xorMaskVar) & LF & "LFSR count time : " & timeStrVal & LF & "reference time/period : " & freqStrVal & LF & "fudge factor : " & fudgeStrVal & LF & "type2FBVar : " & to_string(type2FBVar) & LF & "typeXORVar : " & to_string(typeXORVar) & LF & "# of clock cycles : " & to_string(to_int(countDoneVar)) & LF & "LFSR length : " & to_string(stopVar'length) & LF & "LFSR stop value : " & to_string(stopVar) & LF & LF severity note; file_close(LogFile); -- synopsys translate_on return stopVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return std_logic_vector is constant seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal,f udgeStrVal) downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor",fudgeStrVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft(timeStrVal : string; freqStrVal : string) return std_logic_vector is constant seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor","0"); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft_piped -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft_piped(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor",pipelined_comparator_latency(timeStrVal,freqS trVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft_piped_syn -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft_piped_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor syn",pipelined_comparator_latency(timeStrVal,freqS trVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cft_syn -- -- DESCRIPTION : returns the value of a Type 2 -- Linear Feedback Shift Register (LFSR) -- after the amount -- of time specified using the frequency (or period) -- value passed as a reference -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cft_syn(timeStrVal : string; freqStrVal : string) return std_logic_vector is variable seedVar : std_logic_vector(lfsr_cfth(timeStrVal,freqStrVal," 0") downto 0) := (others => '1'); begin return lfsr_cft(timeStrVal,freqStrVal,seedVar,"Type 2 xor syn","0"); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cfth -- -- DESCRIPTION : -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cfth(timeStrVal : string; freqStrVal : string; fudgeStrVal : string) return integer is variable freqStrVar : std_logic_vector(strval_to_slv_var_base_high(freqS trVal,CFT_BASE_SIZE) downto 0) := strval_to_slv(freqStrVal,CFT_BASE_SIZE); variable timeStrVar : std_logic_vector(strval_to_slv_var_base_high(timeS trVal,CFT_BASE_SIZE) downto 0) := strval_to_slv(timeStrVal,CFT_BASE_SIZE); variable fudgeStrVar : integer := str_to_int(fudgeStrVal); variable resultVar : integer := reduce_high_unsigned(timeStrVar/freqStrVar + fudgeStrVar); variable onesVar : std_logic_vector(resultVar downto 0) := (others => '1'); begin freqStrVar := strval_to_slv(freqStrVal,CFT_BASE_SIZE); timeStrVar := strval_to_slv(timeStrVal,CFT_BASE_SIZE); fudgeStrVar := str_to_int(fudgeStrVal); resultVar := reduce_high_unsigned(timeStrVar/freqStrVar + fudgeStrVar); if (timeStrVar/freqStrVar + fudgeStrVar = onesVar) then resultVar := resultVar + 1; end if; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : lfsr_cfth -- -- DESCRIPTION : -- -- NOTES: -- ------------------------------------------------------------------------------ function lfsr_cfth(timeStrVal : string; freqStrVal : string) return integer is begin return lfsr_cfth(timeStrVal,freqStrVal,"0"); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : max -- -- DESCRIPTION : This function returns the greater of the two values -- passed. -- -- NOTES : ------------------------------------------------------------------------------ function max(int1Val : integer; int2Val : integer) return integer is begin if (int1Val > int2Val) then return int1Val; else return int2Val; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : mult_s -- -- DESCRIPTION : This function multiplies a signed std_logic vector -- value by another signed std_logic_vector value -- -- NOTES : This function is provided for in std_logic_arith ------------------------------------------------------------------------------ function mult_s(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector is variable negVar : std_logic; variable multiplicandVar : std_logic_vector(Multiplicand'length-1 downto 0); variable multiplierVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); variable resultVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); begin multiplicandVar := abs(multiplicand); multiplierVar := ext(abs(Multiplier),multiplierVar'length); negVar := multiplier(multiplier'left) xor multiplicand(multiplicand'left); resultVar := (others => '0'); for loopVar in multiplicandVar'reverse_range loop if (multiplicandVar(loopVar) = '1') then resultVar := resultVar + multiplierVar; end if; multiplierVar := multiplierVar(multiplierVar'high-1 downto 0) & '0'; end loop; if (negVar = '1') then return neg(resultVar); else return resultVar; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : mult_us -- -- DESCRIPTION : This function multiplies an unsigned std_logic vector -- value by another unsigned std_logic_vector value -- -- NOTES : This function is provided for in std_logic_arith ------------------------------------------------------------------------------ function mult_us(Multiplier : std_logic_vector; Multiplicand : std_logic_vector) return std_logic_vector is variable multiplicandVar : std_logic_vector(Multiplicand'length-1 downto 0); variable multiplierVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); variable resultVar : std_logic_vector(Multiplier'length+Multiplicand'le ngth-1 downto 0); begin multiplicandVar := multiplicand; multiplierVar := ext(Multiplier,multiplierVar'length); resultVar := (others => '0'); for loopVar in multiplicandVar'reverse_range loop if (multiplicandVar(loopVar) = '1') then resultVar := resultVar + multiplierVar; end if; multiplierVar := multiplierVar(multiplierVar'high-1 downto 0) & '0'; end loop; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : nat_to_slv (convert natural to std_logic_vector) -- -- DESCRIPTION : This function converts a natural value to a -- std_logic_vector with a range just large enough -- to represent it -- -- NOTES -- ------------------------------------------------------------------------------ function nat_to_slv(natVal : natural) return std_logic_vector is begin return conv_std_logic_vector(natVal,vlfn(natVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : neg -- -- DESCRIPTION : This function toggles the sign of the value passed -- -- NOTES : -- ------------------------------------------------------------------------------ function neg(VectorVal : std_logic_vector) return std_logic_vector is variable oneFndVar : boolean; variable resultVar : std_logic_vector(VectorVal'length-1 downto 0); begin oneFndVar := false; resultVar := VectorVal; resultVar := not resultVar; -- invert all bits resultVar := resultVar + '1'; -- then add one return ResultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : now -- -- DESCRIPTION : This function returns a string representation -- of the current simulation time -- -- NOTES : -- ------------------------------------------------------------------------------ -- synopsys translate_off impure function now return string is variable lineVar : line; variable resultVar : string(1 to time'image(now)'length); begin --Std.TextIO.Write(lineVar, vectorVal); Write(lineVar, time'image(now)); resultVar(lineVar.all'range) := lineVar.all; deallocate(lineVar); return resultVar; end function; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : pipelined_comparator_latency -- -- DESCRIPTION : returns the register compare present in the -- module named : "Pipelined_Comparator" -- -- NOTES: -- -- ------------------------------------------------------------------------------ function pipelined_comparator_latency(busWidthVal : integer) return string is variable latencyVar : integer; -- subtract out the latency of the pipelined comparison variable loopEnableVar : boolean; begin latencyVar := 0; loopEnableVar := TRUE; comparator_latency_computer : while loopEnableVar loop -- compute the expected latency for a pipelined comparator if (2**(2*latencyVar+1) >= busWidthVal) then -- if the current value that latencyVar will have is enough to cover the given vector then stop here loopEnableVar := FALSE; end if; latencyVar := latencyVar + 1; -- minimum latency of 1, increment by 1 before exiting loop end loop comparator_latency_computer; return to_string(-latencyVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : pipelined_comparator_latency -- -- DESCRIPTION : returns the register compare latency needed for the -- module named : "Pipelined_Comparator" -- -- NOTES: -- -- ------------------------------------------------------------------------------ function pipelined_comparator_latency(timeStrVal : string; freqStrVal : string) return string is variable latencyVar : integer; -- subtract out the latency of the pipelined comparison variable loopEnableVar : boolean; variable stopVar : std_logic_vector(cufth(timeStrVal,freqStrVal) downto 0); begin latencyVar := 0; loopEnableVar := TRUE; stopVar := (others => '1'); stop_value_comparator_latency_computer : while loopEnableVar loop -- compute the expected latency for a pipelined stop value comparator if (2**(2*latencyVar+1) >= stopVar'length) then -- if the current value that latencyVar will have is enough to cover the given vector then stop here loopEnableVar := FALSE; end if; latencyVar := latencyVar + 1; -- minimum latency of 1, increment by 1 before exiting loop end loop stop_value_comparator_latency_computer; return to_string(-latencyVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce -- -- DESCRIPTION : This function returns a vector with the extra sign -- bits removed -- -- NOTES : -- ------------------------------------------------------------------------------ function reduce(vectorVal : std_logic_vector) return std_logic_vector is variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(vectorVal'length-1 downto 0); begin resultVar := vectorVal; lengthVar := 0; MSBFound := False; for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar; -- this is the minimum number of bits needed to represent the absolute value. MSBFound := True; end if; end loop; lengthVar := lengthVar + 1; -- And add one for the sign bit return resultVar(lengthVar downto 0); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_high -- -- DESCRIPTION : This function returns an integer value representing -- the vector'high value of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- -- ------------------------------------------------------------------------------ function reduce_high(vectorVal : std_logic_vector) return integer is variable interimVar : std_logic_vector(vectorVal'length-1 downto 0); variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(MAX_VECT_SIZE downto 0); begin interimVar := vectorVal; lengthVar := 0; MSBFound := False; resultVar := sxt(interimVar,resultVar'length); -- sign extend the value passed to the size of the slv variable for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit MSBFound := True; end if; end loop; return lengthVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_high_unsigned -- -- DESCRIPTION : This function returns an integer value representing -- the vector'high value of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- -- ------------------------------------------------------------------------------ function reduce_high_unsigned(vectorVal : std_logic_vector) return integer is variable interimVar : std_logic_vector(vectorVal'length-1 downto 0); variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(MAX_VECT_SIZE downto 0); begin interimVar := vectorVal; lengthVar := 0; MSBFound := False; resultVar := sxt(interimVar,resultVar'length); -- sign extend the value passed to the size of the slv variable for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar; -- this is the minimum number of bits needed to represent the absolute value. MSBFound := True; end if; end loop; return lengthVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_length -- -- DESCRIPTION : This function returns an integer value representing -- the length of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- ------------------------------------------------------------------------------ function reduce_length(vectorVal : std_logic_vector) return integer is begin return reduce_high(vectorVal) + 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_length_unsigned -- -- DESCRIPTION : This function returns an integer value representing -- the length of a sign bit reduced vector -- -- NOTES : This function assumes that vectorVal'low = '0' -- ------------------------------------------------------------------------------ function reduce_length_unsigned(vectorVal : std_logic_vector) return integer is begin return reduce_high_unsigned(vectorVal) + 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : reduce_unsigned -- -- DESCRIPTION : This function returns a vector with all sign -- bits removed -- -- NOTES : -- ------------------------------------------------------------------------------ function reduce_unsigned(vectorVal : std_logic_vector) return std_logic_vector is variable lengthVar : integer; variable MSBFound : boolean; variable resultVar : std_logic_vector(vectorVal'length-1 downto 0); begin resultVar := vectorVal; lengthVar := 0; MSBFound := False; for loopVar in resultVar'range loop -- start at the MSB of the vector and index down if (((resultVar(resultVar'high) = '0' and resultVar(loopVar) = '1') or -- if it's a positive value then look for a bit to be '1' (resultVar(resultVar'high) = '1' and resultVar(loopVar) = '0')) and -- or if it's a negative value look for a bit to be '0' (MSBFound = False)) -- and the MSB hasn't been found yet then -- and if a bit is asserted then lengthVar := loopVar; -- this is the minimum number of bits needed to represent the absolute value. MSBFound := True; end if; end loop; return resultVar(lengthVar downto 0); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : rounddown -- -- DESCRIPTION : This function rounds the first integer value down to the -- next lower multiple of the second integer passed -- -- NOTES : -- ------------------------------------------------------------------------------ function rounddown(int1Val : integer; int2Val : integer) return integer is begin return integer(floor(real(int1Val)/real(int2Val))*real(int2Val)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : roundup -- -- DESCRIPTION : This function rounds the first integer value up to the -- next higher multiple of the second integer passed -- -- NOTES : -- ------------------------------------------------------------------------------ function roundup(int1Val : integer; int2Val : integer) return integer is begin return integer(ceil(real(int1Val)/real(int2Val))*real(int2Val)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : seq (string equality function) -- -- DESCRIPTION : This function returns true if both string values passed -- are identical -- -- NOTES : This function was added because the the synthesis tool -- didn't support a boolean string equality operation test. -- Also, adding a new overloaded operator "=" caused problems -- with the simulator -- ------------------------------------------------------------------------------ function seq(str1Val : string; str2Val : string) return boolean is variable char1Var : character; variable char2Var : character; variable resultVar : boolean; variable str1Var : string(1 to str1Val'length); variable str2Var : string(1 to str2Val'length); begin resultVar := true; str1Var := str1Val; str2Var := str2Val; for loopVar in str1Var'range loop if (str1Var(loopVar) /= str2Var(loopVar)) then resultVar := false; end if; end loop; return resultVar; end function; -------------------------------------------------------------------------------- ---- ---- FUNCTION NAME : shift ---- ---- DESCRIPTION : This function returns a std_logic_vector shifted ---- by the number of integer places specified. This provides ---- an easy way to multiply or divide by 2^(natVal) ---- ---- ---- NOTES ---- -------------------------------------------------------------------------------- --function shift(vectorVal : std_logic_vector; -- intVal : integer) return std_logic_vector is -- variable resultVar : std_logic_vector(vectorVal'length-1 downto 0); --begin -- resultVar := vectorVal; -- resultVar := (others => '0'); -- resultVar(resultVar'high downto resultVar'high-vectorVal'length+1) := resultVar; -- return resultVar; --end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : shl (shift left) -- -- DESCRIPTION : This function returns a std_logic_vector shifted left -- by the number of binary places specified. This provides -- an easy way to multiply by 2^(natVal) -- -- -- NOTES -- ------------------------------------------------------------------------------ function shl(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector is variable interimVar : std_logic_vector(vectorVal'length-1 downto 0); variable resultVar : std_logic_vector(vectorVal'length+natVal-1 downto 0); begin interimVar := vectorVal; resultVar := (others => '0'); resultVar(resultVar'high downto resultVar'high-vectorVal'length+1) := interimVar; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd -- -- DESCRIPTION : This function converts an unsigned, decending range, -- std logic vector value into a -- packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number of BCD digits passed to the function. -- -- NOTES -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to -- ------------------------------------------------------------------------------ function slv_to_bcd(vectorVal : std_logic_vector; BCD_DigitsVal : integer) return std_logic_vector is type resultArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector of std_logic_vector(4*BCD_DigitsVal-1 downto 0); -- array width is determined by the number of BCD digits to output variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if the next BCD Digit is computed without carry from the current BCD value variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if the next BCD Digit is computed with carry from the current BCD value variable InnrLoopVar : integer := 0; -- inner loop index variable variable OutrLoopVar : integer := 0; -- outer loop index variable variable ResultVar : resultArrayType; -- BCD value result variable variable VectorVar : std_logic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; ResultVar(0) := (others => '0'); -- set the initial entry in the results array to zero for OutrLoopVar in VectorVar'high downto 0 loop -- start at the MSB of the std logic vector input and work down CarryVar(0) := VectorVar(OutrLoopVar); -- read in the next bit of the slv input into the lowest carry bit for InnrLoopVar in 0 to BCD_DigitsVal-1 loop -- start at the LSB of the BCD output BCD_WoCarVar := ResultVar(VectorVar'length - OutrLoopVar -1) -- read the results of the previous calculation (4*InnrLoopVar+3 downto 4*InnrLoopVar); BCD_WiCarVar := BCD_WoCarVar - "0101"; -- compute the result for the current BCD digit if a carry to the next digit will be needed if (BCD_WoCarVar > "0100") then -- if the digit is 5 or greater ("0101") then the result of the binary shift left "10100" = decimal 16, which is to great to represent in one BCD digit so then CarryVar(InnrLoopVar+1) := '1'; -- we carry a digit to the next BCD digit ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- and we use the lesser value for the current digit along with the carry value from the previous BCD digit else -- otherwise the digit is small enough to be represented in one BCD digit when a binary shift in is performed CarryVar(InnrLoopVar+1) := '0'; ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- so we write the value to the result variable along with any carry value from a previous BCD digit end if; end loop; end loop; return ResultVar(VectorVar'high+1); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd -- -- DESCRIPTION : This function converts an unsigned, decending range, -- binary value into a packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) -- -- "width mismatch" errors are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector is type resultArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector of std_logic_vector(4*dpfslvr(vectorVal)-1 downto 0); -- array width is determined by the number of BCD digits to output variable CarryVar : std_logic_vector (dpfslvr(vectorVal) downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if no carry to the next BCD Digit is needed variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if carry to the next BCD Digit is needed variable InnrLoopVar : integer := 0; -- inner loop index variable variable OutrLoopVar : integer := 0; -- outer loop index variable variable ResultVar : resultArrayType; -- BCD value result variable variable VectorVar : std_logic_vector(vectorVal'length-1 downto 0); begin VectorVar := vectorVal; ResultVar(0) := (others => '0'); -- set the initial entry in the results array to zero for OutrLoopVar in VectorVar'high downto 0 loop -- start at the MSB of the std logic vector input and work down CarryVar(0) := VectorVar(OutrLoopVar); -- read in the next bit of the slv input into the lowest carry bit for InnrLoopVar in 0 to CarryVar'high-1 loop -- start at the LSB of the BCD output BCD_WoCarVar := ResultVar(VectorVar'length - OutrLoopVar -1) -- read the results of the previous calculation (4*InnrLoopVar+3 downto 4*InnrLoopVar); BCD_WiCarVar := BCD_WoCarVar - "0101"; -- compute the result for the current BCD digit if a carry to the next digit will be needed if (BCD_WoCarVar > "0100") then -- if the digit is 5 or greater ("0101") then the result of the binary shift left "10100" = decimal 16, which is to great to represent in one BCD digit so then CarryVar(InnrLoopVar+1) := '1'; -- we carry a digit to the next BCD digit ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- and we use the lesser value for the current digit along with the carry value from the previous BCD digit else -- otherwise the digit is small enough to be represented in one BCD digit when a binary shift in is performed CarryVar(InnrLoopVar+1) := '0'; ResultVar(VectorVar'length - OutrLoopVar) (4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- so we write the value to the result variable along with any carry value from a previous BCD digit end if; end loop; end loop; return ResultVar(VectorVar'high+1); -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd_pipe -- -- DESCRIPTION : This function converts an unsigned, decending range, -- binary value into a packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it. -- it is for use in pipelined implementations where -- the binary coded decimal output is registered -- and passed back to the function along with the binary -- vector input to be shifted out of its MSB -- register and into the function as a new bit. -- -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) -- -- "width mismatch" errors here are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function slv_to_bcd_pipe( BCD_RVal : std_logic_vector; -- registered output of this function fed back in MSB_Val : std_logic; -- msb of binary value being shifted in BCD_DigitsVal : integer) return std_logic_vector is -- binary coded decimal arithmetic shift left variable BCDVar : std_logic_vector(BCD_RVal'length-1 downto 0); variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0); -- the # of carry bits is determined by the number of BCD digits variable BCD_WoCarVar : std_logic_vector(3 downto 0); variable BCD_WiCarVar : std_logic_vector(3 downto 0); variable ResultVar : std_logic_vector(4*BCD_DigitsVal-1 downto 0); begin BCDVar := BCD_RVal; for loopVar in 0 to BCD_DigitsVal-1 loop CarryVar(0) := MSB_Val; BCD_WoCarVar := BCDVar(4*loopVar+3 downto 4*loopVar); BCD_WiCarVar := BCD_WoCarVar - "0101"; if (BCD_WoCarVar > "0100") then CarryVar(loopVar+1) := '1'; ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WiCarVar(2 downto 0) & CarryVar(loopVar); else CarryVar(loopVar+1) := '0'; ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WoCarVar(2 downto 0) & CarryVar(loopVar); end if; end loop; return ResultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_int -- -- DESCRIPTION : This function converts a string to an integer -- -- NOTES : -- ------------------------------------------------------------------------------ function str_to_int(stringVal : string) return integer is variable decPlace : integer := 1; variable stringVar : string(1 to stringVal'length); variable negVar : boolean; -- used to indicate whether or not the string represents a negative number variable resultVar : integer; variable vectorParseVar : character; begin negVar := false; resultVar := 0; stringVar := stringVal; for loopVar in stringVar'range loop vectorParseVar := stringVar(loopVar); case vectorParseVar is when '-' => negVar := true; when '0' => resultVar := (resultVar * 10) + 0; when '1' => resultVar := (resultVar * 10) + 1; when '2' => resultVar := (resultVar * 10) + 2; when '3' => resultVar := (resultVar * 10) + 3; when '4' => resultVar := (resultVar * 10) + 4; when '5' => resultVar := (resultVar * 10) + 5; when '6' => resultVar := (resultVar * 10) + 6; when '7' => resultVar := (resultVar * 10) + 7; when '8' => resultVar := (resultVar * 10) + 8; when '9' => resultVar := (resultVar * 10) + 9; when '.' => if (negVar) then -- ignore everything after a decimal point return -resultVar; else return resultVar; end if; when others => end case; end loop; if (negVar) then -- ignore everything after a decimal point return -resultVar; else return resultVar; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_line -- -- DESCRIPTION : This function converts a string to a line -- -- NOTES : -- ------------------------------------------------------------------------------ -- synopsys translate_off function str_to_line(strVal : string) return line is variable lineVar : line; begin --Std.TextIO.Write(lineVar, vectorVal); Write(lineVar, strVal); return lineVar; end function; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_led -- -- DESCRIPTION : This function converts a Seven Segment LED -- string of any length to a std_logic_vector -- -- NOTES : if the CAVal boolean input is true the output will -- be for a Common Anode (1=off) display, otherwise it will -- be for a Common Cathode (1=on)display. -- -- _____ -- | a | -- f| |b -- |_____| -- | g | -- e| |c -- |_____| -- d -- -- "width mismatch" errors here are due to improper sizing of the vector -- that this function is assigned to ------------------------------------------------------------------------------ function str_to_led(stringVal : string; CAVal : boolean) return std_logic_vector is variable stringVar : string(stringVal'length downto 1); variable resultVar : std_logic_vector(7*StringVal'length downto 1); variable vectorParseVar : character; begin stringVar := stringVal; for loopVar in StringVar'range loop vectorParseVar := StringVar(loopVar); case vectorParseVar is -- Illuminated -- character Segment -- shown abcdefg when ' ' => resultVar(7*loopVar downto 7*loopVar-6) := "0000000"; when '"' => resultVar(7*loopVar downto 7*loopVar-6) := "0100010"; when ''' => resultVar(7*loopVar downto 7*loopVar-6) := "0100000"; when '-' => resultVar(7*loopVar downto 7*loopVar-6) := "0000001"; when '/' => resultVar(7*loopVar downto 7*loopVar-6) := "0100101"; when '0' | 'D' => resultVar(7*loopVar downto 7*loopVar-6) := "1111110"; when '1' => resultVar(7*loopVar downto 7*loopVar-6) := "0110000"; when '2' => resultVar(7*loopVar downto 7*loopVar-6) := "1101101"; when '3' => resultVar(7*loopVar downto 7*loopVar-6) := "1111001"; when '4' => resultVar(7*loopVar downto 7*loopVar-6) := "0110011"; when '5' | 'S' => resultVar(7*loopVar downto 7*loopVar-6) := "1011011"; when '6' => resultVar(7*loopVar downto 7*loopVar-6) := "1011111"; when '7' => resultVar(7*loopVar downto 7*loopVar-6) := "1110010"; when '8' | 'B' => resultVar(7*loopVar downto 7*loopVar-6) := "1111111"; when '9' => resultVar(7*loopVar downto 7*loopVar-6) := "1110011"; when '=' => resultVar(7*loopVar downto 7*loopVar-6) := "0001001"; when '?' => resultVar(7*loopVar downto 7*loopVar-6) := "1100101"; when 'A' => resultVar(7*loopVar downto 7*loopVar-6) := "1110111"; when 'C' => resultVar(7*loopVar downto 7*loopVar-6) := "1001110"; when 'E' => resultVar(7*loopVar downto 7*loopVar-6) := "1001111"; when 'F' => resultVar(7*loopVar downto 7*loopVar-6) := "1000111"; when 'G' => resultVar(7*loopVar downto 7*loopVar-6) := "1011110"; when 'H' => resultVar(7*loopVar downto 7*loopVar-6) := "0110111"; when 'I' => resultVar(7*loopVar downto 7*loopVar-6) := "0000110"; when 'J' => resultVar(7*loopVar downto 7*loopVar-6) := "1111100"; when 'L' => resultVar(7*loopVar downto 7*loopVar-6) := "0001110"; when 'O' => resultVar(7*loopVar downto 7*loopVar-6) := "1111110"; when 'P' => resultVar(7*loopVar downto 7*loopVar-6) := "1100111"; when 'T' => resultVar(7*loopVar downto 7*loopVar-6) := "1000110"; when 'U' => resultVar(7*loopVar downto 7*loopVar-6) := "0111110"; when 'Y' => resultVar(7*loopVar downto 7*loopVar-6) := "0100111"; when 'Z' => resultVar(7*loopVar downto 7*loopVar-6) := "1101101"; when '\' => resultVar(7*loopVar downto 7*loopVar-6) := "0010011"; when ']' => resultVar(7*loopVar downto 7*loopVar-6) := "1111000"; when '^' => resultVar(7*loopVar downto 7*loopVar-6) := "1100010"; when '_' => resultVar(7*loopVar downto 7*loopVar-6) := "0001000"; when 'b' => resultVar(7*loopVar downto 7*loopVar-6) := "0011111"; when 'c' => resultVar(7*loopVar downto 7*loopVar-6) := "0001101"; when 'd' => resultVar(7*loopVar downto 7*loopVar-6) := "0111101"; when 'g' => resultVar(7*loopVar downto 7*loopVar-6) := "1111011"; when 'h' => resultVar(7*loopVar downto 7*loopVar-6) := "0010111"; when 'j' => resultVar(7*loopVar downto 7*loopVar-6) := "0111100"; when 'l' => resultVar(7*loopVar downto 7*loopVar-6) := "0111000"; when 'n' => resultVar(7*loopVar downto 7*loopVar-6) := "0010101"; when 'o' => resultVar(7*loopVar downto 7*loopVar-6) := "0011101"; when 'r' => resultVar(7*loopVar downto 7*loopVar-6) := "0000101"; when 'u' => resultVar(7*loopVar downto 7*loopVar-6) := "0011100"; when '¬' => resultVar(7*loopVar downto 7*loopVar-6) := "0010001"; when '¯' => resultVar(7*loopVar downto 7*loopVar-6) := "1000000"; when '°' => resultVar(7*loopVar downto 7*loopVar-6) := "1100011"; when others => end case; end loop; if (CAVal) then return not resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to else return resultVar; -- "width mismatch" errors here are due to improper sizing of the vector that this function is assigned to end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : str_to_slv -- -- DESCRIPTION : This function converts an std_logic_vector value (in string form) -- of any length to a std_logic_vector -- -- NOTES : -- -- ------------------------------------------------------------------------------ function str_to_slv(stringVal : string) return std_logic_vector is variable resultVar : std_logic_vector(MAX_VECT_SIZE downto 0) := (others => '0'); variable stringParseVar : character; variable stringVar : string(1 to stringVal'length) := stringVal; variable validBitCountVar : integer := 0; begin straight_to_slv : for loopVar in stringVar'reverse_range loop stringParseVar := stringVar(loopVar); case stringParseVar is when '0' => resultVar(validBitCountVar) := '0'; validBitCountVar := validBitCountVar + 1; when '1' => resultVar(validBitCountVar) := '1'; validBitCountVar := validBitCountVar + 1; when others => end case; end loop straight_to_slv; return resultVar(validBitCountVar-1 downto 0); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strh -- -- DESCRIPTION : This function returns the high value of a string vector -- -- -- NOTES -- -- ------------------------------------------------------------------------------ function strh(stringVal : string) return integer is begin return stringVal'high; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv -- -- DESCRIPTION : This function converts an integer value (in string form) -- of any length to a std_logic_vector -- -- NOTES : -- -- ------------------------------------------------------------------------------ function strval_to_slv(stringVal : string) return std_logic_vector is begin return strval_to_slv(stringVal,-15); -- default to 1fs time base end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv -- -- DESCRIPTION : This function has 3 modes of operations depending on what -- it is presented with. -- 1. It will convert an integer, in string form, into a -- standard logic vector. -- 2. It will convert a time or period value, in string form, -- into a standard logic vector. -- 3. It will convert a frequency value, in string form, -- into a standard logic vector of that frequency's period. -- -- NOTES : This function uses the integer value passed as the exponent -- of the timebase to use for its computations. -- It supports both positive and negative numbers -- as well as positive and negative exponents. It supports -- multiple time unit per string as long as there are no -- exponents used. No other units may start with the -- character 's' unless the "ec" detection portion -- of the "seconds" unit portion is uncommented -- and 's' is no longer used as a unit for "seconds" -- -- Time units supported -- -- 0.000 000 000 000 000 000 000 001 yoctosecond [ ys ] 10^(-24) -- 0.000 000 000 000 000 000 001 zeptosecond [ zs ] 10^(-21) -- 0.000 000 000 000 000 001 attosecond [ as ] 10^(-1 -- 0.000 000 000 000 001 femtosecond [ fs ] 10^(-15) -- 0.000 000 000 001 [ trillionth ] picosecond [ ps ] 10^(-12) -- 0.000 000 001 [ billionth ] nanosecond [ ns ] 10^(-9) -- 0.000 001 [ millionth ] microsecond [ µs ] 10^(-6) -- 0.001 [ thousandth ] millisecond [ ms ] 10^(-3) -- 0.01 [ hundredth ] centisecond [ cs ] 10^(-2) -- 1.0 second [ s or sec ] 10^(0) -- 60.0 minute [ min ] 10^(0) -- 3600.0 hour [ hr ] 10^(0) -- 86,400.0 day [ day ] 10^(0) -- -- -- Frequency units supported -- -- 1 hertz [ hz ] 10^(0) -- 1,000 kilohertz [ khz ] 10^(3) -- 1,000,000 megahertz [ mhz ] 10^(6) -- 1,000,000,000 gigahertz [ ghz ] 10^(9) -- 1,000,000,000,000 terahertz [ thz ] 10^(12) -- 1,000,000,000,000,000 petahertz [ phz ] 10^(15) -- 1,000,000,000,000,000,000 exahertz [ ehz ] 10^(1 -- 1,000,000,000,000,000,000,000 zetahertz [ zhz ] 10^(21) -- 1,000,000,000,000,000,000,000,000 yottahertz [ yhz ] 10^(24) -- -- EXAMPLE "1 day, 3 hrs, 15.298 seconds" -- "66,000,000 Hz" "66,000,000.000 Hz" "66 MHz" "66E6 Hz" "66E+6 Hz" "66.000E+6 Hz" -- "66,000,000 us" "66,000,000.000 us" "66 us" "66E6 us" "66E+6 us" "66.000E+6 us" -- -- ------------------------------------------------------------------------------ function strval_to_slv(stringVal : string; intVal : integer) return std_logic_vector is constant \10\ : std_logic_vector(3 downto 0) := "1010"; -- 10 constant \60\ : std_logic_vector(5 downto 0) := "111100"; -- 60 constant \3600\ : std_logic_vector(11 downto 0) := "111000010000"; -- 3600 constant \86400\ : std_logic_vector(16 downto 0) := "10101000110000000"; -- 86,400 (solar day) variable baseVar : integer; -- exponent of the timebase i.e. 1fs = 1E-15 seconds so the timebase = 15 variable decPlacesVar : integer; -- used to count how many numbers are after the decimal point variable decPntFndVar : boolean; -- used to flag whether or not a decimal point was found in the string variable expFndVar : boolean; -- used to flag that the exponent has been reached so that the rest of the string value will not be interpreted as part of the base value variable expVar : integer; -- used to indicated the exponent value variable freqUnitFndVar : boolean; -- used to flag whether or not the string represents a frequency variable negVar : boolean; -- used to flag whether or not the string represents a negative number variable resultVar : std_logic_vector(MAX_VECT_SIZE+16 downto 0); variable result2Var : std_logic_vector(MAX_VECT_SIZE+16 downto 0); -- used to store a result from a secondary value such as would be encounter when a value such as "1 hr 10 mins" is passed to the function variable scndTimeFndVar : boolean; -- used to indicate a second time value was found variable stringParseVar : character; -- character currently under test variable stringVar : string(1 to stringVal'length+4); -- slightly larger because string is addessed beyond the current loop to test for units variable timeBaseVar : std_logic_vector(MAX_VECT_SIZE+16 downto 0); variable timeUnitFndVar : boolean; -- used to flag that a time unit was found (days, hrs, mins, secs) variable validBitCountVar : integer := 0; begin baseVar := -intVal; decPntFndVar := false; -- initialize to decimal point not found yet decPlacesVar := 0; expFndVar := false; -- initialize to exponent point not found yet expVar := 0; freqUnitFndVar := false; -- initialize to frequency units not found yet negVar := false; -- initialize to negative sign not found yet resultVar := (others => '0'); result2Var := (others => '0'); scndTimeFndVar := false; -- initialize to secont time value not found yet stringVar := stringVal & " "; -- tack on few extra spaces for padding so that it is possible to address beyond the current loop variable timeUnitFndVar := false; timeBaseVar := ext("01",timeBaseVar'length); for loopVar in 1 to baseVar loop timeBaseVar := mult_us(timeBaseVar(MAX_VECT_SIZE+12 downto 0), \10\); -- this value will contain the time base (in binary) when this loop completes (10^30 for a baseVar of 30) end loop; for loopVar in stringVar'range loop -- this loop parses the string value passed to this function from left to right stringParseVar := stringVar(loopVar); if (scndTimeFndVar) then resultVar := resultVar; -- if a second value has been found then just wait here for the loop to complete else case stringParseVar is when '-' => if (not decPntFndvar and not expFndVar and not freqUnitFndVar and not timeUnitFndVar) then -- expect the sign to be near the front of the string negVar := true; end if; when '0' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then -- if the decimal point was found and we're not reading an exponent then decPlacesVar := decPlacesVar + 1; -- consider this to be a number after the decimal point end if; if (not expFndVar) then -- if we are not reading the exponent then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 0; -- factor in the next digit end if; end if; when '1' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 1; end if; end if; when '2' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 2; end if; end if; when '3' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 3; end if; end if; when '4' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 4; end if; end if; when '5' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 5; end if; end if; when '6' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 6; end if; end if; when '7' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 7; end if; end if; when '8' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 8; end if; end if; when '9' => if (freqUnitFndVar) then resultVar := resultVar; -- do nothing elsif (timeUnitFndVar) then -- if we've already found a time unit then this must be a second time value result2Var := ext(strval_to_slv(stringVar(loopVar to stringVar'length),intVal),result2Var'length); -- pass the rest of the string to the next instance of the function scndTimeFndVar := true; else if (decPntFndVar and not expFndVar) then decPlacesVar := decPlacesVar + 1; end if; if (not expFndVar) then resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\) + 9; end if; end if; when 'e' | 'E' => -- exponent if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- exahertz unit found for loopVar in 1 to 18 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not expFndVar and not freqUnitFndVar and not timeUnitFndVar) -- if we haven't already found an exponent, frequency unit, or time unit then expFndVar := true; -- mark that we've found it expVar := str_to_int(stringVar(loopVar to stringVal'length)); -- and capture its value end if; when '.' => decPntFndVar := true; -- mark the position of the decimal point when 'y' | 'Y' => -- yoctosecond 10^-24 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- yoctosecond unit found for loopVar in 1 to baseVar-24 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- yottahertz unit found for loopVar in 1 to 24 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'z' | 'Z' => -- zeptosecond 10^-21 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- zeptosecond unit found for loopVar in 1 to baseVar-21 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- zettahertz unit found for loopVar in 1 to 21 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'a' | 'A' => -- attosecond 10^-18 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- attosecond unit found for loopVar in 1 to baseVar-18 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'f' | 'F' => -- femtosecond 10^-15 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- femtosecond unit found for loopVar in 1 to baseVar-15 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'p' | 'P' => -- picosecond 10^-12 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- picosecond unit found for loopVar in 1 to baseVar-12 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- petahertz unit found for loopVar in 1 to 15 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'n' | 'N' => -- nanosecond 10^-9 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- nanosecond unit found for loopVar in 1 to baseVar-9 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'u' | 'U' => -- microsecond 10^-6 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- microsecond unit found for loopVar in 1 to baseVar-6 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'm' | 'M' => -- millisecond 10^-3 if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 's') or (stringVar(loopVar+1) = 'S'))) then timeUnitFndVar := true; -- millisecond unit found for loopVar in 1 to baseVar-3 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "in")) or (seq(stringVar(loopVar+1 to loopVar+2), "iN")) or (seq(stringVar(loopVar+1 to loopVar+2), "In")) or (seq(stringVar(loopVar+1 to loopVar+2), "IN")))) then timeUnitFndVar := true; -- minute unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; resultVar := mult_us(resultVar(MAX_VECT_SIZE+10 downto 0), \60\); elsif (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- megahertz unit found for loopVar in 1 to 6 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 's' | 'S' => if (not freqUnitFndVar and not timeUnitFndVar) -- and --((seq(stringVar(loopVar+1 to loopVar+2), "ec")) or -- (seq(stringVar(loopVar+1 to loopVar+2), "eC")) or -- (seq(stringVar(loopVar+1 to loopVar+2), "Ec")) or -- (seq(stringVar(loopVar+1 to loopVar+2), "EC")))) then timeUnitFndVar := true; -- second unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'h' | 'H' => if (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 'r') or (stringVar(loopVar+1) = 'R'))) then timeUnitFndVar := true; -- hour unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; resultVar := mult_us(resultVar(MAX_VECT_SIZE+4 downto 0), \3600\); elsif (not freqUnitFndVar and not timeUnitFndVar and ((stringVar(loopVar+1) = 'z') or (stringVar(loopVar+1) = 'Z'))) then freqUnitFndVar := true; end if; when 'd' | 'D' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "ay")) or (seq(stringVar(loopVar+1 to loopVar+2), "aY")) or (seq(stringVar(loopVar+1 to loopVar+2), "Ay")) or (seq(stringVar(loopVar+1 to loopVar+2), "AY")))) then timeUnitFndVar := true; -- day unit found for loopVar in 1 to baseVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; resultVar := mult_us(resultVar(MAX_VECT_SIZE-1 downto 0), \86400\); end if; when 'g' | 'G' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- gigahertz unit found for loopVar in 1 to 9 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 'k' | 'K' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- kilohertz unit found for loopVar in 1 to 3 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when 't' | 'T' => if (not freqUnitFndVar and not timeUnitFndVar and ((seq(stringVar(loopVar+1 to loopVar+2), "hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "hZ")) or (seq(stringVar(loopVar+1 to loopVar+2), "Hz")) or (seq(stringVar(loopVar+1 to loopVar+2), "HZ")))) then freqUnitFndVar := true; -- terahertz unit found for loopVar in 1 to 12 loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; end if; when others => end case; end if; end loop; if (expVar >= 0) then -- if it's a positive exponent then perform a multiplication loop for loopVar in 1 to expVar loop resultVar := mult_us(resultVar(MAX_VECT_SIZE+12 downto 0), \10\); end loop; else -- if it's a negative exponent then perform a division loop for loopVar in 1 to (-expVar) loop resultVar := resultVar / \10\; end loop; end if; if (decPntFndVar) then -- if a decimal point was present in the value then for loopVar in 1 to decPlacesVar loop -- scale the output accordingly resultVar := resultVar / \10\; end loop; end if; resultVar := resultVar + result2Var; -- add on any secondary value if (freqUnitFndVar) then -- the the string is a frequency value then resultVar := timeBaseVar / resultVar; -- invert it to convert it to a period value before returning end if; if (negVar and not timeUnitFndVar) then -- the the string is a negative value and its not a time value then resultVar := neg(resultVar); -- negate the result end if; return reduce(resultVar); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv_high -- -- DESCRIPTION : This function converts an integer value string -- of any length to a std_logic_vector -- -- NOTES -- -- ------------------------------------------------------------------------------ function strval_to_slv_high(stringVal : string) return integer is begin return reduce_high(strval_to_slv(stringVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : strval_to_slv_var_base_high -- -- DESCRIPTION : This function converts an integer value string -- of any length to a std_logic_vector -- -- NOTES -- -- ------------------------------------------------------------------------------ function strval_to_slv_var_base_high(stringVal : string; intVal : integer) return integer is begin return reduce_high(strval_to_slv(stringVal,intVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : sxt2 (sign extend) -- -- DESCRIPTION : This function returns a standard logic vector, -- padded with zeros, to the length specified by intVal -- -- NOTES : -- ------------------------------------------------------------------------------ function sxt2(vectorVal : std_logic_vector; natVal : natural) return std_logic_vector is variable zeroVar : std_logic_vector(natVal - vectorVal'length - 1 downto 0) := (others => '0'); variable oneVar : std_logic_vector(natVal - vectorVal'length - 1 downto 0) := (others => '1'); variable vectorVar : std_logic_vector(vectorVal'length - 1 downto 0); begin vectorVar := vectorVal; if (vectorVar(vectorVar'high) = '1') then if (vectorVar'length >= natVal) then return vectorVar; else return oneVar & vectorVar; end if; else if (vectorVar'length >= natVal) then return vectorVar; else return zeroVar & vectorVar; end if; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_int -- -- DESCRIPTION : conv_integer function repackaged -- -- NOTES -- ------------------------------------------------------------------------------ function to_int(vectorVal : std_logic_vector) return integer is begin return conv_integer(vectorVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_period -- -- DESCRIPTION : This function returns a one cycle period value for -- a given frequency -- -- NOTES timeVar must be larger than the simulator resolution -- and is limited by the integer that can be created from -- time'pos of it's value -- -- the funtion does not work with Synplify 7.7 ------------------------------------------------------------------------------ --function to_period(freqVal : frequency) return time is -- variable resultVar : time; --begin -- resultVar := 1E9/frequency'pos(freqVal) * 1 ns; -- max of 2147.483647 ns for Precision Synthesis -- return resultVar; --end function; -- new Physical types not supported by XST -- synopsys translate_off function to_period(freqVal : frequency) return time is variable resultVar : time; variable timeVar : time := 1 ms; variable divVar : real := real(1 sec/timeVar); begin if (frequency'pos(freqVal) > 2_147_483_647) then assert FALSE report "Frequency value passed to function is greater than 2,147,483,647 when converted to base units." severity warning; end if; resultVar := divVar/real(frequency'pos(freqVal)) * timeVar; -- see "NOTES" return resultVar; end function; -- synopsys translate_off ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_period -- -- DESCRIPTION : This function returns a one cycle period value for -- a given frequency -- -- NOTES timeVar must be larger than the simulator resolution -- and is limited by the integer that can be created from -- time'pos of it's value -- -- the funtion does not work with Synplify 7.7 ------------------------------------------------------------------------------ --function to_period(freqVal : string) return time is -- variable resultVar : time; --begin -- resultVar := 1E9/frequency'pos(freqVal) * 1 ns; -- max of 2147.483647 ns for Precision Synthesis -- return resultVar; --end function; --function to_period(freqVal : string) return time is -- constant timeVar : time := 1 ms; -- variable divVar : real := real(1 sec/timeVar); -- variable freqVar : frequency; -- variable resultVar : time; --begin -- freqVar := cft(freqVal); -- if (frequency'pos(freqVal) > 2_147_483_647) then -- assert FALSE -- report "Frequency value passed to function is greater than 2,147,483,647 when converted to base units." -- severity warning; -- end if; -- resultVar := divVar/real(frequency'pos(freqVal)) * timeVar; -- see "NOTES" -- return resultVar; --end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (boolean) -- -- DESCRIPTION : This function returns a string value representing the -- boolean value passed to it. -- NOTES -- ------------------------------------------------------------------------------ function to_string(boolVal : boolean) return string is begin if (boolVal) then return "TRUE"; else return "FALSE"; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (integer) -- -- DESCRIPTION : This function returns a string value representing the -- integer value passed to it. -- NOTES -- ------------------------------------------------------------------------------ ------ synopsys translate_off --function to_string(intVal : integer) return string is -- variable lineVar : line; -- variable resultVar : string(1 to cfi(intVal)); --begin -- --Std.TextIO.Write(lineVar, intVal); -- Write(lineVar, integer'Image(intVal)); -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ------ synopsys translate_on function to_string(intVal : integer) return string is begin return integer'Image(intVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (real) -- -- DESCRIPTION : This function returns a string value representing the -- integer value passed to it. -- NOTES -- ------------------------------------------------------------------------------ ---- synopsys translate_off --function to_string(realVal : real) return string is -- variable lengthVar : natural; -- variable lineVar : line; -- variable resultVar : string(1 to real'Image(realVal)'length); --begin -- --Std.TextIO.Write(lineVar, intVal); -- Write(lineVar, real'Image(realVal)); -- lengthVar := lineVar.all'length; -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ---- synopsys translate_on function to_string(realVal : real) return string is begin return real'Image(realVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (time) -- -- DESCRIPTION : This function returns a string value representing the -- time value passed to it. -- -- NOTES : -- ------------------------------------------------------------------------------ ---- synopsys translate_off --function to_string(timeVal : time) return string is -- variable lineVar : line; -- variable resultVar : string(1 to time'image(timeVal)'length); --begin -- --Std.TextIO.Write(lineVar, vectorVal); -- Write(lineVar, time'image(timeVal)); -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ---- synopsys translate_on function to_string(timeVal : time) return string is begin return time'image(timeVal); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : to_string (vector) -- -- DESCRIPTION : This function returns a string value representing the -- vector value passed to it. -- NOTES -- -- 'U', -- Uninitialized -- 'X', -- Forcing Unknown -- '0', -- Forcing 0 -- '1', -- Forcing 1 -- 'Z', -- High Impedance -- 'W', -- Weak Unknown -- 'L', -- Weak 0 -- 'H', -- Weak 1 -- '-' -- Don't care ------------------------------------------------------------------------------ -- synthesis tool un-friendly version ---- synopsys translate_off --function to_string(vectorVal : std_logic_vector) return string is -- variable lineVar : line; -- variable resultVar : string(1 to vectorVal'length); --begin -- --Std.TextIO.Write(lineVar, vectorVal); -- Write(lineVar, vectorVal); -- resultVar(lineVar.all'range) := lineVar.all; -- deallocate(lineVar); -- return resultVar; --end function; ---- synopsys translate_on -- synthesis tool friendly version function to_string(vectorVal : std_logic_vector) return string is variable lineVar : line; variable resultVar : string(1 to vectorVal'length); variable vectorVar : std_logic_vector(1 to vectorVal'length); begin vectorVar := vectorVal; for loopVar in vectorVar'range loop if (vectorVar(loopVar) = 'U') then -- 'U', -- Uninitialized resultVar(loopVar) := 'U'; elsif (vectorVar(loopVar) = 'X') then -- 'X', -- Forcing Unknown resultVar(loopVar) := 'X'; elsif (vectorVar(loopVar) = '0') then -- '0', -- Forcing 0 resultVar(loopVar) := '0'; elsif (vectorVar(loopVar) = '1') then -- '1', -- Forcing 1 resultVar(loopVar) := '1'; elsif (vectorVar(loopVar) = 'Z') then -- 'Z', -- High Impedance resultVar(loopVar) := 'Z'; elsif (vectorVar(loopVar) = 'W') then -- 'W', -- Weak Unknown resultVar(loopVar) := 'W'; elsif (vectorVar(loopVar) = 'L') then -- 'L', -- Weak 0 resultVar(loopVar) := 'L'; elsif (vectorVar(loopVar) = 'H') then -- 'H', -- Weak 1 resultVar(loopVar) := 'H'; elsif (vectorVar(loopVar) = '-') then -- '-' -- Don't care resultVar(loopVar) := '-'; end if; end loop; return resultVar; end function; -------------------------------------------------------------------------------- ---- ---- PROCEDURE NAME : transpose ---- ---- DESCRIPTION : This procedure returns the transpose of an array ---- ---- NOTES : column 1 -> row 1 ---- column 2 -> row 2 ---- -------------------------------------------------------------------------------- --procedure( transpose(arrayVal : array_type) return array_type is -- variable resultVar : std_ulogic_vector(vectorVal'range); --begin -- for loopVar in vectorVal'low to vectorVal'high loop -- resultVar(resultVar'high-loopVar) := vectorVal(loopVar); -- end loop; -- return resultVar; --end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vhfi (vector high for integer) -- -- DESCRIPTION : This function returns the 'high value to be used -- in the range declaration of a vector used to -- represent the integer value passed to it. -- -- WARNING: This function assumes the rest of the -- range declaration of the vector -- will be "downto 0" -- -- NOTES : see vlfi for more information -- -- EXAMPLE : ------------------------------------------------------------------------------ function vhfi(intVal : integer) return natural is begin return vlfi(intVal) - 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vhfn (vector high for natural) -- -- DESCRIPTION : This function returns the 'high value to be used -- in the range declaration of a vector used to -- represent the natural value passed to it. -- -- WARNING: This function assumes the rest of the -- range declaration of the vector -- will be "downto 0" -- -- NOTES : see vlfn for more information -- -- EXAMPLE : ------------------------------------------------------------------------------ function vhfn(natVal : natural) return natural is begin return vlfn(natVal) - 1; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vlfi (vector length for integer) -- -- DESCRIPTION : This function returns an integer representing the -- length of the vector required to represent -- the integer value passed to it. This includes -- the sign bit; hence the "resultVar := loopVar + 1;" -- -- NOTES : type integer is range -2147483648 to 2147483647; -- This function can be used in code intended for synthesis -- Using a 31 bit variable strips off the sign bit that -- the conversion function generates. This allows us -- to place the sign bit in the new location at the top -- of the vector. -- -- EXAMPLE : -2147483648 passed, convertion to logic vector gives -- 0000000000000000000000000000000. Bit 31 is '0' and -- a sign bit is needed so 31 + 1 = 32 bits are needed to -- represent this value -- -- given intVal = 32 -- slvVar is assigned 0000000000000000000000000100000 -- "if" condition becomes true for loopVar = 6 -- result is 7 (6 bits to represent 32, plus the sign bit) ------------------------------------------------------------------------------ function vlfi(intVal : integer) return natural is variable resultVar : natural; variable slvVar : std_logic_vector(31 downto 1); -- range of 31 downto 1 used because the numbering is correct for the positional location of the bits begin slvVar := conv_std_logic_vector(intVal,slvVar'length); -- convert the integer passed to the function to a 31 bit logic vector if (intVal > 0) then -- if the integer is positive then for loopVar in slvVar'range loop -- start at the top of the vector and index down if (slvVar(loopVar) = '1') then -- and if a bit is asserted then return loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit end if; end loop; elsif (intVal = 0) then -- '0' has no value and, therefore, needs no sign bit return 1; elsif (intVal = -1) then -- '-1' is a special case which contains no zeros so the following algorithm would fail. return 2; elsif (intVal < -1) then -- if the integer is negative then for loopVar in slvVar'range loop -- start at the top of the vector and index down if (slvVar(loopVar) = '0') then -- and if a bit is asserted then return loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit end if; end loop; end if; return resultVar; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vlfn (vector length for natural) -- -- DESCRIPTION : This function returns an integer representing the -- length of the vector required to represent -- the natural value passed to it. There is no -- sign bit needed so "resultVar := loopVar;" -- -- NOTES : subtype natural is integer range 0 to 2_147_483_647; -- This function can be used in code intended for synthesis -- -- EXAMPLE : given natVal = 32 -- slvVar is assigned 0000000000000000000000000100000 -- "if" condition becomes true for loopVar = 6 -- result is 6 (6 bits to represent 32, no sign bit needed) ------------------------------------------------------------------------------ function vlfn(natVal : natural) return natural is variable resultVar : natural; variable slvVar : std_logic_vector(31 downto 1); begin slvVar := conv_std_logic_vector(natVal,slvVar'length); if (natVal > 2_147_483_647) then assert false report "value exceeds 2,147,483,647" severity warning; return 0; elsif (natVal > 0) then for loopVar in slvVar'range loop if (slvVar(loopVar) = '1') then return loopVar; end if; end loop; else return 1; end if; end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vrfi (vector range for integer) -- -- DESCRIPTION : This function returns a std_logic_vector of the same range -- required to represent the integer value passed to it. -- This includes the sign bit; -- -- NOTES : subtype natural is integer range 0 to 2_147_483_647; -- This function can be used in code intended for synthesis -- ------------------------------------------------------------------------------ function vrfi(intVal : integer) return std_logic_vector is variable slvVar : std_logic_vector(vhfi(intVal) downto 0); attribute slv_high : natural; attribute slv_low : natural; attribute slv_range : natural; attribute slv_high of slvVar : variable is slvVar'high; attribute slv_low of slvVar : variable is slvVar'low; --attribute slv_range of slvVar : variable is slvVar'range; begin return slvVar; end function; -------------------------------------------------------------------------------- ---- ---- FUNCTION NAME : vrfi (vector range for integer) ---- ---- DESCRIPTION : This function returns a std_logic_vector of the same range ---- required to represent the integer value passed to it. ---- This includes the sign bit; ---- hence the "resultVar := loopVar + 1;" ---- ---- NOTES : subtype natural is integer range 0 to 2_147_483_647; ---- This function cannot be used in code intended for synthesis ---- -------------------------------------------------------------------------------- ---- synopsys translate_off --function vrfi(intVal : integer) return std_logic_vector is -- type slv_ptr is access std_logic_vector; -- variable size : slv_ptr; -- variable resultVar : natural; -- variable slvVar : std_logic_vector(31 downto 1); --begin -- slvVar := conv_std_logic_vector(intVal,slvVar'length); -- convert the integer passed to the function to a 31 bit logic vector -- if (intVal > 0) then -- if the integer is positive then -- for loopVar in slvVar'range loop -- start at the top of the vector and index down -- if (slvVar(loopVar) = '1') then -- and if a bit is asserted then -- resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit -- exit; -- end if; -- end loop; -- elsif (intVal = 0) then -- '0' has no value and, therefore, needs no sign bit -- resultVar := 1; -- elsif (intVal = -1) then -- '-1' is a special case which contains no zeros so the following algorithm would fail. -- resultVar := 2; -- elsif (intVal < -1) then -- if the integer is negative then -- for loopVar in slvVar'range loop -- start at the top of the vector and index down -- if (slvVar(loopVar) = '0') then -- and if a bit is asserted then -- resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit -- exit; -- end if; -- end loop; -- end if; -- size := new std_logic_vector(resultVar-1 downto 0); ---- return size.all'range; -- return size.all; -- deallocate(size); --end function; ---- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : vrfn (vector range for natural) -- -- DESCRIPTION : This function returns an std_logic_vector representing the -- length of the vector required to represent -- the natural value passed to it. -- -- NOTES : subtype natural is integer range 0 to 2_147_483_647; -- This function can be used in code intended for synthesis -- ------------------------------------------------------------------------------ function vrfn(natVal : natural) return std_logic_vector is variable slvVar : std_logic_vector(vhfn(natVal) downto 0); attribute slv_high : natural; attribute slv_low : natural; attribute slv_range : natural; attribute slv_high of slvVar : variable is slvVar'high; attribute slv_low of slvVar : variable is slvVar'low; --attribute slv_range of slvVar : variable is slvVar'range; begin return slvVar; end function; -------------------------------------------------------------------------------- ---- ---- FUNCTION NAME : vrfn (vector range for natural) ---- ---- DESCRIPTION : This function returns an std_logic_vector representing the ---- length of the vector required to represent ---- the natural value passed to it. ---- ---- NOTES : subtype natural is integer range 0 to 2_147_483_647; ---- This function cannot be used in code intended for synthesis ---- -------------------------------------------------------------------------------- ---- synopsys translate_off --function vrfn(natVal : natural) return std_logic_vector is -- type slv_ptr is access std_logic_vector; -- variable size : slv_ptr; -- variable resultVar : natural; -- variable slvVar : std_logic_vector(31 downto 1); --begin -- slvVar := conv_std_logic_vector(natVal,slvVar'length); -- if (natVal > 0) then -- for loopVar in slvVar'range loop -- if (slvVar(loopVar) = '1') then -- resultVar := loopVar; -- exit; -- end if; -- end loop; -- else -- resultVar := 1; -- end if; -- size := new std_logic_vector(resultVar-1 downto 0); -- return size.all; -- deallocate(size); --end function; ---- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : xnor_reduce (multiple input xnor gate) -- -- DESCRIPTION : -- -- NOTES : -- ------------------------------------------------------------------------------ function xnor_reduce (vectorVal : std_logic_vector) return std_logic is begin return not(xor_reduce(vectorVal)); end function; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : xor_reduce (multiple input xor gate) -- -- DESCRIPTION : -- -- NOTES : -- ------------------------------------------------------------------------------ function xor_reduce (vectorVal : std_logic_vector) return std_logic is variable MSB, LSB : std_logic; variable halfway : integer; variable vectorVar : std_logic_vector(vectorVal'length-1 downto 0); variable result : std_logic := '0'; begin vectorVar := vectorVal; if (vectorVar'length >= 1) then if (vectorVar'length = 1) then result := vectorVar(vectorVar'high); elsif (vectorVar'length = 2) then result := "xor"(vectorVar(vectorVar'high),vectorVar(vectorVa r'low)); else halfway := (vectorVar'length + 1) / 2; -- determine the halfway point MSB := xor_reduce(vectorVar(vectorVar'high downto halfway)); -- call the function recursively LSB := xor_reduce(vectorVar(halfway - 1 downto vectorVar'low)); -- call the function recursively result := "xor"(MSB, LSB); end if; end if; return result; end function; ------------------------------------------------------------------------------ -- -- Procedures -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a 50% duty cycle clock with the specified -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( constant clkFreqSig : in frequency; signal clkSig : out std_logic) is variable posPeriodVar : time := (to_period(clkFreqSig) * 50.0) / 100; variable negPeriodVar : time := to_period(clkFreqSig) - posPeriodVar; begin while true loop clkSig <= '1'; wait for posPeriodVar; clkSig <= '0'; wait for negPeriodVar; end loop; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a 50% duty cycle clock with the specified -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; signal clkSig : out std_logic) is variable posPeriodVar : time := (to_period(clkFreqSig) * 50.0) / 100; variable negPeriodVar : time := to_period(clkFreqSig) - posPeriodVar; begin while clkEnSig loop clkSig <= '1'; wait for posPeriodVar; clkSig <= '0'; wait for negPeriodVar; end loop; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a clock -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( signal clkEnSig : in boolean; signal clkPeriodSig : in time; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic) is variable posPeriodVar : time; variable negPeriodVar : time; begin posPeriodVar := (clkPeriodSig * clkDutySig) / 100; negPeriodVar := clkPeriodSig - posPeriodVar; if (clkResetSig) then clkSig <= '1'; elsif (clkEnSig) then if (clkSig = '1') then clkSig <= '0' after posPeriodVar; else clkSig <= '1' after negPeriodVar; end if; end if; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- PROCEDURE NAME : clock_gen -- -- DESCRIPTION : generate a clock -- -- NOTES -- ------------------------------------------------------------------------------ -- synopsys translate_off procedure clkgen( signal clkEnSig : in boolean; signal clkFreqSig : in frequency; constant clkDutySig : in real; signal clkResetSig : in boolean; signal clkSig : inout std_logic) is variable posPeriodVar : time; variable negPeriodVar : time; begin posPeriodVar := (to_period(clkFreqSig) * clkDutySig) / 100; negPeriodVar := to_period(clkFreqSig) - posPeriodVar; if (clkResetSig) then clkSig <= '1'; elsif (clkEnSig) then if (clkSig = '1') then clkSig <= '0' after posPeriodVar; else clkSig <= '1' after negPeriodVar; end if; end if; end procedure; -- synopsys translate_on ------------------------------------------------------------------------------ -- -- FUNCTION NAME : FF -- -- DESCRIPTION : simple flip flop procedure -- -- NOTES : synthesizeable -- ------------------------------------------------------------------------------ procedure FF ( signal Clk : in std_logic; signal Rst : in std_logic; signal D : in std_logic_vector; signal Q : out std_logic_vector) is variable zeros : std_logic_vector(Q'range) := (others => '0'); begin if (Rst = '1') then Q <= zeros; elsif Rising_Edge(Clk) then Q <= D; end if; end procedure; ------------------------------------------------------------------------------ -- -- FUNCTION NAME : slv_to_bcd -- -- DESCRIPTION : This function converts an unsigned, decending range, -- binary value into a packed binary coded decimal (BCD) -- standard logic vector and returns the result in -- the number BCD digits required to represent the maximum -- unsigned value possible in the vector passed to it. -- it is for use in pipelined implementations where -- the binary coded decimal output is registered -- and passed back to the function along with the binary -- vector input to be shifted out of its MSB -- register and into the function as a new bit. -- -- -- NOTES -- BCD_DigitsVal -> dpfslvr(vectorVal) ------------------------------------------------------------------------------ procedure slv_to_bcd( signal BCD_RIn : in std_logic_vector; signal BinIn : in std_logic_vector; signal BinFBIn : in std_logic_vector; signal ClkIn : in std_logic; constant BCD_DigitsVal : in integer; signal EnIn : in std_logic; signal RstLowIn : in std_logic; signal BCD_ROut : out std_logic_vector; signal Bin_ROut : out std_logic_vector; -- registed, shifted version of BinIn signal DoneOut : out std_logic) is constant BCD_ZEROS : std_logic_vector(BCD_ROut'range) := (others => '0'); constant BIN_ZEROS : std_logic_vector(BinIn'range) := (others => '0'); variable BCD_Var : std_logic_vector(BCD_ROut'range); variable BCD_RVar : std_logic_vector(BCD_ROut'range); begin if (RstLowIn = '0' or EnIn = '0') then BCD_ROut <= BCD_ZEROS; BCD_RVar := BIN_ZEROS; Bin_ROut <= BinIn; DoneOut <= '0'; elsif rising_edge(ClkIn) then Bin_ROut <= BinFBIn(BinFBIn'high-1 downto BinFBIn'low) & '0'; if (BinFBIn = BIN_ZEROS) then BCD_ROut <= BCD_RIn; DoneOut <= '1'; else BCD_ROut <= slv_to_bcd_pipe(BCD_RIn,BinFBIn(BinFBIn'high),BCD_ DigitsVal); DoneOut <= '0'; end if; end if; end procedure; ------------------------------------------------------------------------------ end extension_pack; ------------------------------------------------------------------------------ -- end of extension pack -- test bench starts below -- synopsys translate_off ------------------------------------------------------------------------------ -- Extension Pack test bench ------------------------------------------------------------------------------ library ieee, extension_lib; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use extension_lib.extension_pack.all; --use extension_lib.extension_pack_constants.all; use ieee.std_logic_textio.all; use std.textio.all; entity extension_pack_tb is end extension_pack_tb; ------------------------------------------------------------------------------ architecture behavioral of extension_pack_tb is ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- Signal declarations ------------------------------------------------------------------------------ begin star_operator_test1 : process variable slvVar : std_logic_vector(2 downto 0) := "111"; begin assert (eq(7*slvVar,"0110001")) -- 7*7 = 49 report "*1 error # 1 " & LF & to_string("0110001") & " : expected" & LF & to_string(7*slvVar) & " : actual" severity error; wait; end process; star_operator_test2 : process variable slvVar : std_logic_vector(2 downto 0) := "111"; begin assert (eq(slvVar*7,"0110001")) -- 7*7 = 49 report "*2 error # 1 " & LF & to_string("0110001") & " : expected" & LF & to_string(slvVar*7) & " : actual" severity error; wait; end process; --function "/"(DividendVal : std_logic_vector; -- DivisorVal : std_logic_vector) return std_logic_vector; slash1_operator_test : process constant slvVar : std_logic_vector(6 downto 0) := "0110001"; constant \7\ : std_logic_vector(6 downto 0) := "0000111"; begin assert (eq("0110001"/"111",\7\)) -- 49/7 = 7 report "slash1_operator_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string("0110001"/"111") & " : actual" severity error; wait; end process; --function "/"(DividendVal : std_logic_vector; -- DivisorVal : integer) return std_logic_vector; slash2_operator_test : process constant slvVar : std_logic_vector(6 downto 0) := "0110001"; begin assert (eq(slvVar/7,"0000111")) -- 49/7 = 7 report "slash2_operator_test error # 2 " & LF & to_string("0000111") & " : expected" & LF & to_string(slvVar/7) & " : actual" severity error; wait; end process; --function "/"(DividendVal : string; -- DivisorVal : integer) return std_logic_vector; slash3_operator_test : process constant var : string := "49"; begin assert (eq(var/7,"0000111")) -- 49/7 = 7 report "slash3_operator_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string(var/7) & " : actual" severity error; wait; end process; --function bcd_to_led(slvVal : std_logic_vector ; -- CAVal : boolean) return std_logic_vector; -- binary coded decimal to seven segment LED conversion bcd_to_led1_test : process constant slv1Var : std_logic_vector := x"0123456789ABCDEF"; variable slv2Var : std_logic_vector(27 downto 0); begin assert (bcd_to_led(slv1Var,true) = "0000001100111100100100000110100110001001000100000 00011010000000000110011101110011111100111001111011 0011111000111") -- 123456789ABCDEF = report "bcd_to_led_test error # 1 " & LF & to_string("000000110011110010010000011010011000100 10001000000001101000000000011001110111001111110011 10011110110011111000111") & " : expected" & LF & to_string(bcd_to_led(slv1Var,true)) & " : actual" severity error; assert (bcd_to_led(slv1Var,false) = "1111110011000011011011111001011001110110111011111 11100101111111111001100010001100000011000110000100 1100000111000") -- 123456789ABCDEF = report "bcd_to_led_test error # 2 " & LF & to_string("111111001100001101101111100101100111011 01110111111110010111111111100110001000110000001100 01100001001100000111000") & " : expected" & LF & to_string(bcd_to_led(slv1Var,false)) & " : actual" severity error; slv2Var := bcd_to_led(x"3210",False); -- 3210 assert (slv2Var = "1111001110110101100001111110") report "bcd_to_led_test error # 1 " severity error; slv2Var := bcd_to_led(x"7654",False); -- 7654 assert (slv2Var = "1110010101111110110110110011") report "bcd_to_led_test error # 2 " severity error; slv2Var := bcd_to_led(x"1098",False); -- 1098 assert (slv2Var = "0110000111111011100111111111") report "bcd_to_led_test error # 3 " severity error; slv2Var := bcd_to_led(x"3210",True); -- 3210 assert (slv2Var = "0000110001001010011110000001") report "bcd_to_led_test error # 4 " severity error; slv2Var := bcd_to_led(x"7654",True); -- 7654 assert (slv2Var = "0001101010000001001001001100") report "bcd_to_led_test error # 5 " severity error; slv2Var := bcd_to_led(x"1098",True); -- 1098 assert (slv2Var = "1001111000000100011000000000") report "bcd_to_led_test error # 6 " severity error; wait; end process; --function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed bcd_to_slv_test : process constant slvVar : std_logic_vector := x"0123456789ABCDEF"; begin assert (bcd_to_slv(slvVar) = "011100000100100010000110000111101101001110111111" ) -- 123456789ABCDEF = 123456790123455 report "bcd_to_slv_test error # 1 " & LF & to_string("011100000100100010000110000111101101001 110111111") & " : expected" & LF & to_string(bcd_to_slv(slvVar)) & " : actual" severity error; assert (bcd_to_slv(x"1234567890") = "01001001100101100000001011010010") -- 1234567890 = report "bcd_to_slv_test error # 2 " & LF & to_string("01001001100101100000001011010010") & " : expected" & LF & to_string(bcd_to_slv(slvVar)) & " : actual" severity error; assert (bcd_to_slv(x"ABCDEF") = "100010010010001111111") -- ABCDEF (1123455) report "bcd_to_slv_test error # 3 " & LF & to_string("100010010010001111111") & " : expected" & LF & to_string(bcd_to_slv(x"ABCDEF")) & " : actual" severity error; wait; end process; --function bcd_to_slv_pipe(BCD_RVal : std_logic_vector; -- BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value --function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector; -- repackaging of "To_StdLogicVector" function bv_to_slv_test : process constant bvVar : bit_vector := x"0123456789ABCDEF"; begin assert (bv_to_slv(bvVar) = x"0123456789ABCDEF") -- 123456789ABCDEF = 123456790123455 report "bv_to_slv_test error # 1 " & LF & to_string(x"0123456789ABCDEF") & " : expected" & LF & to_string(bv_to_slv(bvVar)) & " : actual" severity error; assert (bv_to_slv(x"123456789ABCDEF") = x"0123456789ABCDEF") -- 123456789ABCDEF = 123456790123455 report "bv_to_slv_test error # 2 " & LF & to_string(x"0123456789ABCDEF") & " : expected" & LF & to_string(bv_to_slv(x"123456789ABCDEF")) & " : actual" severity error; wait; end process; --function cdft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_down_for_time2_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cdft("8 ms ","1 kHz") = slvVar) report "count_down_for_time2_test error # 1 " & LF & to_string("0111") & " : expected" & LF & to_string(cdft("8 ms ","1 kHz")) & " : actual" severity error; assert (cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz")) = "0110") report "count_down_for_time2_test error # 2 " & LF & to_string("0110") & " : expected" & LF & to_string(cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz"))) & " : actual" severity error; assert (cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz"))'length = 4) report "count_down_for_time2_test error # 3 " & LF & to_string(4) & " : expected" & LF & to_string(cdft("8 ms ","1 kHz",cdfth("8 ms ","1 kHz"))'length) & " : actual" severity error; wait; end process; --function cdft(timeStrVal : string; -- freqStrVal : string; -- natVal : natural) return std_logic_vector; -- count for the time specified (minus a count of 2 for latency) using the frequency (or period) value passed as a reference and the natural value passed as a length for the vector (if it will fit in a vector that size) --function cdfth(timeStrVal : string; -- freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference count_down_for_time_high_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cdfth("1 us ","1E-15 yHz") = 10) report "count_down_for_time_high_test error # 1 " & LF & to_string(10) & " : expected" & LF & to_string(cdfth("1 us ","1E-15 yHz")) & " : actual" severity error; assert (cdfth("8 ms ","1 kHz") = 3) report "count_down_for_time_high_test error # 2 " & LF & to_string(3) & " : expected" & LF & to_string(cdfth("8 ms ","1 kHz")) & " : actual" severity error; wait; end process; --function ceil(RealVal : in real ) return real; -- rounds a real value up the the next highest real integer ceil_test : process begin assert (ceil(-9.999999) = -9.0) report "ceil_test error # 1 " & LF & to_string(-9.0) & " : expected" & LF & to_string(ceil(-9.999999)) & " : actual" severity error; assert (ceil(9.999999) = 10.0) report "ceil_test error # 2 " & LF & to_string(10.0) & " : expected" & LF & to_string(ceil(9.999999)) & " : actual" severity error; wait; end process; --function cfi(intVal : integer) return natural; cfi_test : process begin assert (cfi(-1000) = 5) report "cfi_test error # 1 " & LF & "5 : expected" & LF & to_string(cfi(-1000)) & " : actual" severity error; assert (cfi(-10000) = 6) report "cfi_test error # 2 " & LF & "6 : expected" & LF & to_string(cfi(-10000)) & " : actual" severity error; assert (cfi(1000) = 4) report "cfi_test error # 3 " & LF & "4 : expected" & LF & to_string(cfi(1000)) & " : actual" severity error; assert (cfi(-100_000) = 7) report "cfi_test error # 4 " & LF & "7 : expected" & LF & to_string(cfi(-100_000)) & " : actual" severity error; assert (cfi(100_000) = 6) report "cfi_test error # 5 " & LF & "6 : expected" & LF & to_string(cfi(100_000)) & " : actual" severity error; assert (cfi(-9999999) = report "cfi_test error # 6 " & LF & to_string( & " : expected" & LF &to_string(cfi(-9999999)) & " : actual" severity error; assert (cfi(9999999) = 7) report "cfi_test error # 7 " & LF & to_string(7) & " : expected" & LF & to_string(cfi(9999999)) & " : actual" severity error; wait; end process; --function cft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_for_time_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(20 downto 0); begin assert (cft(CNTTIME,SYSCLKFREQ) = "100111010101101100110100000000") report "count_for_time_test error # 1 " & LF & to_string("100111010101101100110100000000") & " : expected" & LF & to_string(cft(CNTTIME,SYSCLKFREQ)) & " : actual" severity error; assert (cft("1 min","66MHz") = "11101100000010001100111000000000") report "count_for_time_test error # 2 " & LF & to_string("11101100000010001100111000000000") & " : expected" & LF & to_string(cft("1 min","66MHz")) & " : actual" severity error; assert (cft("1 hr","66MHz") = "11011101010010000100000100100000000000") report "count_for_time_test error # 3 " & LF & to_string("11011101010010000100000100100000000000" ) & " : expected" & LF & to_string(cft("1 hr","66MHz")) & " : actual" severity error; assert (cft("1 day","66MHz") = "01010010111110110001100001101100000000000000" ) report "count_for_time_test error # 4 " & LF & to_string("010100101111101100011000011011000000000 00000") & " : expected" & LF & to_string(cft("1 day","66MHz")) & " : actual" severity error; assert (cft("1 day","66MHz")+cft("1 hr","66MHz")+cft("1 min","66MHz")+cft("1 sec","66MHz")+cft("1 ms","66MHz")+cft("1 us","66MHz")+cft("1 ns","66MHz")+cft("1 ps","66MHz")+cft("1 fs","66MHz") = "01010110011111110011100011111110110010010010" ) report "count_for_time_test error # 5 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 day","66MHz")+cft("1 hr","66MHz")+cft("1 min","66MHz")+cft("1 sec","66MHz")+cft("1 ms","66MHz")+cft("1 us","66MHz")+cft("1 ns","66MHz")+cft("1 ps","66MHz")+cft("1 fs","66MHz")) & " : actual" & LF & to_string(cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs","66MHz")) & " : actual" severity error; assert (cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs","66MHz") = "01010110011111110011100011111110110010010010" ) report "count_for_time_test error # 6 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 day","66MHz")+cft("1 hr","66MHz")+cft("1 min","66MHz")+cft("1 sec","66MHz")+cft("1 ms","66MHz")+cft("1 us","66MHz")+cft("1 ns","66MHz")+cft("1 ps","66MHz")+cft("1 fs","66MHz")+cft("1 as","66MHz")+cft("1 zs","66MHz")+cft("1 ys","66MHz")) & " : actual" & LF & to_string(cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz")) & " : actual" severity error; assert (cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz") = "01010110011111110011100011111110110010010010" ) report "count_for_time_test error # 7 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz")) & " : actual" severity error; assert (cft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz") = "0111000111001100111101101010001010110100000001010 01") report "count_for_time_test error # 8 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz")) & " : actual" severity error; assert (cft("1 sec","1E-3 kHz") = "01") report "count_for_time_test error # 9 " & LF & to_string("01") & " : expected" & LF & to_string(cft("1 sec","1E-3 kHz")) & " : actual" severity error; assert (cft("1 sec","1E-18 eHz") = "01") report "count_for_time_test error # 10 " & LF & to_string("01") & " : expected" & LF & to_string(cft("1 sec","1E-18 eHz")) & " : actual" severity error; assert (cft("1 ns ","1E-15 yHz") = "01") report "count_for_time_test error # 11 " & LF & to_string("010101100111111100111000111111101100100 10010") & " : expected" & LF & to_string(cft("1 ns ","1E-15 yHz")) & " : actual" severity error; assert (cft("1 us ","1E-15 yHz") = "01111101000") report "count_for_time_test error # 12 " & LF & to_string("01111101000") & " : expected" & LF & to_string(cft("1 us ","1E-15 yHz")) & " : actual" severity error; slvVar := ext(cft("20 ms ","50 MHz"),21); assert (ext(cft("20 ms ","50 MHz"),21) = "011110100001001000000") report "count_for_time_test error # 13 " & LF & to_string("01111101000") & " : expected" & LF & to_string(ext(cft("20 ms ","50 MHz"),21)) & " : actual" severity error; wait; end process; --function cfth(timeStrVal : string; -- freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference count_for_time_high_test : process begin assert (cfth("1 us ","1E-15 yHz") = 10) report "count_for_time_high_test error # 1 " & LF & to_string(10) & " : expected" & LF & to_string(cfth("1 us ","1E-15 yHz")) & " : actual" severity error; wait; end process; --function cfth(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_for_time_high_test2 : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cfth("8 ms ","1 kHz") = 4) report "count_for_time_high_test2 error # 1 " & LF & to_string(4) & " : expected" & LF & to_string(cfth("8 ms ","1 kHz")) & " : actual" severity error; wait; end process; --function clkcnt(freq1StrVal : string; -- freq2StrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference clock_count_test : process begin assert (clkcnt("1 kHz","50 MHz") = "110000110100111") report "clock_count_test error # 1 " & LF & to_string("110000110100111") & " : expected" & LF & to_string(clkcnt("1 kHz","50 MHz")) & " : actual" severity error; wait; end process; --function conv_to_hex(vectorVal : bit_vector) return string; -- bit_vector to hexadecimal conversion conv_to_hex_test1 : process variable testVar : bit_vector(63 downto 0) := x"0123456789ABCDEF"; begin assert (conv_to_hex(testVar) = "0123456789ABCDEF") report "conv_to_hex_test1 error # 1 " & LF & "0123456789ABCDEF" & " : expected" & LF & conv_to_hex(testVar) & " : actual" severity error; wait; end process; --function conv_to_hex(vectorVal : std_logic_vector) return string; -- std_logic_vector to hexadecimal conversion conv_to_hex_test2 : process variable testVar : std_logic_vector(63 downto 0) := x"0123456789ABCDEF"; begin assert (conv_to_hex(testVar) = "0123456789ABCDEF") report "conv_to_hex_test2 error # 1 " & LF & "0123456789ABCDEF" & " : expected" & LF & conv_to_hex(testVar) & " : actual" severity error; wait; end process; --function conv_to_hex(vectorVal : std_ulogic_vector) return string; -- std_ulogic_vector to hexadecimal conversion conv_to_hex_test3 : process variable testVar : std_logic_vector(63 downto 0) := x"0123456789ABCDEF"; begin assert (conv_to_hex(testVar) = "0123456789ABCDEF") report "conv_to_hex_test3 error # 1 " & LF & "0123456789ABCDEF" & " : expected" & LF & conv_to_hex(testVar) & " : actual" severity error; wait; end process; --function cslv(int1Val : integer; -- int2Val : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" -- repackaged functions not tested --function cslv(sigVal : signed; -- intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" -- repackaged functions not tested --function cslv(usgVal : unsigned; -- intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector" -- repackaged functions not tested --function cuft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- count for the time specified using the frequency (or period) value passed as a reference count_up_for_time_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(20 downto 0); begin assert (cuft(CNTTIME,SYSCLKFREQ) = "100111010101101100110011111111") report "count_up_for_time_test error # 1 " & LF & to_string("100111010101101100110011111111") & " : expected" & LF & to_string(cuft(CNTTIME,SYSCLKFREQ)) & " : actual" severity error; assert (cuft("1 min","66MHz") = "11101100000010001100110111111111") report "count_for_time_test error # 2 " & LF & to_string("11101100000010001100110111111111") & " : expected" & LF & to_string(cuft("1 min","66MHz")) & " : actual" severity error; assert (cuft("1 hr","66MHz") = "11011101010010000100000100011111111111") report "count_up_for_time_test error # 3 " & LF & to_string("11011101010010000100000100011111111111" ) & " : expected" & LF & to_string(cuft("1 hr","66MHz")) & " : actual" severity error; assert (cuft("1 day","66MHz") = "1010010111110110001100001101011111111111111") report "count_up_for_time_test error # 4 " & LF & to_string("101001011111011000110000110101111111111 1111") & " : expected" & LF & to_string(cuft("1 day","66MHz")) & " : actual" severity error; assert (cuft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs","66MHz") = "1010110011111110011100011111110110010010001") report "count_up_for_time_test error # 6 " & LF & to_string("101011001111111001110001111111011001001 0001") & " : expected" & LF & to_string(cuft("1 day","66MHz")+cuft("1 hr","66MHz")+cuft("1 min","66MHz")+cuft("1 sec","66MHz")+cuft("1 ms","66MHz")+cuft("1 us","66MHz")+cuft("1 ns","66MHz")+cuft("1 ps","66MHz")+cuft("1 fs","66MHz")+cuft("1 as","66MHz")+cuft("1 zs","66MHz")+cuft("1 ys","66MHz")) & " : actual" & LF & to_string(cuft("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs 1as 1zs 1ys","66MHz")) & " : actual" severity error; assert (cuft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz") = "1110001110011001111011010100010101101000000010100 0") report "count_up_for_time_test error # 8 " & LF & to_string("111000111001100111101101010001010110100 00000101000") & " : expected" & LF & to_string(cuft("1 ns 1 ps 1 fs 1as 1zs 1ys","1YHz")) & " : actual" severity error; assert (cuft("1 sec","1E-3 kHz") = "0") report "count_up_for_time_test error # 9 " & LF & to_string("00") & " : expected" & LF & to_string(cuft("1 sec","1E-3 kHz")) & " : actual" severity error; assert (cuft("1 sec","1E-18 eHz") = "0") report "count_up_for_time_test error # 10 " & LF & to_string("00") & " : expected" & LF & to_string(cuft("1 sec","1E-18 eHz")) & " : actual" severity error; assert (cuft("1 ns ","1E-15 yHz") = "0") report "count_up_for_time_test error # 11 " & LF & to_string("0") & " : expected" & LF & to_string(cuft("1 ns ","1E-15 yHz")) & " : actual" severity error; assert (cuft("1 us ","1E-15 yHz") = "1111100111") report "count_up_for_time_test error # 12 " & LF & to_string("1111100111") & " : expected" & LF & to_string(cuft("1 us ","1E-15 yHz")) & " : actual" severity error; slvVar := ext(cuft("20 ms ","50 MHz"),21); assert (ext(cuft("20 ms ","50 MHz"),25) = "0000011110100001000111111") report "count_up_for_time_test error # 13 " & LF & to_string("0000011110100001000111111") & " : expected" & LF & to_string(ext(cuft("20 ms ","50 MHz"),25)) & " : actual" severity error; wait; end process; --function cufth(timeStrVal : string; -- freqStrVal : string) return integer; -- returns the high value to be used in the range declaration of a vector used to represent the time specified using the frequency (or period) value passed as a reference count_up_for_time_high_test : process variable CNTTIME : string(1 to 6) := "10 sec"; variable SYSCLKFREQ : string(1 to 5) := "66MHz"; variable slvVar : std_logic_vector(3 downto 0) := "0110"; -- 8 - 2 = 6 begin assert (cufth("1 us ","1E-15 yHz") = 9) report "count_up_for_time_high_test error # 1 " & LF & to_string(9) & " : expected" & LF & to_string(cufth("1 us ","1E-15 yHz")) & " : actual" severity error; assert (cufth("8 ms ","1 kHz") = 2) report "count_up_for_time_high_test2 error # 1 " & LF & to_string(2) & " : expected" & LF & to_string(cufth("8 ms ","1 kHz")) & " : actual" severity error; wait; end process; --function dpfi(intVal : integer) return natural; -- returns the number of decimal places for an integer value --function dpfi_syn(intVal : integer) return natural; -- returns the number of decimal places for an integer value --function dpfr(realVal : real) return natural; -- returns the number of decimal places to the left of the decimal point for a real value --function dpfslvr(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the full range of the std_logic_vector passed --function dpfslvv(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the value of the std_logic_vector passed --function eq(vector1Val : std_logic_vector; -- vector2Val : std_logic_vector) return boolean; -- equality check function that is sensitive to vector length --function ext2(vectorVal : std_logic_vector; -- natVal : natural) return std_logic_vector; -- returns a standard logic vector, padded with zeros, to the length specified by intVal unless the vector is already longer than that ext_test : process constant slvVar : std_logic_vector := "0111"; variable slv1Var : std_logic_vector(11 downto 0); variable slv2Var : std_logic_vector(11 downto 0); variable slv3Var : std_logic_vector(slv1Var'range); begin slv1Var := ext2(int_to_slv(1000),slv1Var'length); slv2Var := ext2(int_to_slv(6),slv2Var'length); assert (ext2(slvVar,7) = "0000111") -- 7 bits report "ext_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string(ext2(slvVar,7)) & " : actual" severity error; assert (ext2(slvVar,4) = "0111") -- 4 bits report "ext_test error # 2 " & LF & to_string("0000111") & " : expected" & LF & to_string(ext2(slvVar,4)) & " : actual" severity error; assert (ext2(slvVar,4)'length = 4) -- 4 bits report "ext_test error # 3 " & LF & to_string(4) & " : expected" & LF & to_string(ext2(slvVar,4)'length) & " : actual" severity error; wait; end process; --function flip(vectorVal : bit_vector) return bit_vector; -- returns a bit_vector with all the bits in the reverse order --function flip(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector with all the bits in the reverse order --function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector; -- returns a std_ulogic_vector with all the bits in the reverse order --function floor(RealVal : in real ) return real; -- rounds a real value down the the next lowest real integer floor_test : process begin assert (floor(-9.999999) = -10.0) report "floor_test error # 1 " & LF & to_string(-10.0) & " : expected" & LF & to_string(floor(-9.999999)) & " : actual" severity error; assert (floor(9.999999) = 9.0) report "floor_test error # 2 " & LF & to_string(9.0) & " : expected" & LF & to_string(floor(9.999999)) & " : actual" severity error; assert (integer(floor(real(4)/real(2)))-1 = 1) report "floor_test error # 3 " & LF & to_string(1) & " : expected" & LF & to_string(integer(floor(real(4)/real(2)))-1) & " : actual" severity error; wait; end process; --function hex_to_slv(stringVal : string) return std_logic_vector; -- converts a Hexadeximal string to a standard logic vector --function int_to_slv(intVal : integer) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the integer value passed int_to_slv_test : process begin assert (int_to_slv(1) = "01") report "int_to_slv_test error # 1 " & LF & to_string(01) & " : expected" & LF & to_string(int_to_slv(1)) & " : actual" severity error; assert (int_to_slv(0) = "0") report "int_to_slv_test error # 2 " & LF & to_string(0) & " : expected" & LF & to_string(int_to_slv(0)) & " : actual" severity error; assert (int_to_slv(0)'high = 0) report "int_to_slv_test error # 2a " & LF & to_string(0) & " : expected" & LF & to_string(int_to_slv(0)'high) & " : actual" severity error; assert (int_to_slv(-1) = "11") report "int_to_slv_test error # 3 " & LF & "11" & " : expected" & LF & to_string(int_to_slv(-1)) & " : actual" severity error; wait; end process; --function itoa(intVal : integer) return string; -- common integer to string conversion function --function lfsr(vectorVal : std_ulogic_vector) return std_logic; -- returns the input to a Linear Feedback Shift Register (LFSR) using x^6 + x^5 + x^3 + x^2 + 1 as the primitive feedback polynomial lfsr_test : process constant OUTPUT_FILE : string := LOG_PATH & "lfsr_test_logfile" & LOG_EXT; variable LogFileLine : line; file LogFile : text; --open write_mode is OUTPUT_FILE; variable FileStatus : file_open_status; type LFSRAccessType is access std_logic_vector; type SeedAccessType is access std_logic_vector; variable LFSRVar : LFSRAccessType; variable SeedVar : SeedAccessType; variable LFSRTestVar : std_logic_vector(7 downto 0); begin file_open(LogFile, external_name => OUTPUT_FILE, open_kind => write_mode); write(logFileLine, string'("LFSR Maximal repeats")); writeLine(LogFile,logFileLine); write(logFileLine, string'("length length? after")); writeLine(LogFile,logFileLine); write(logFileLine, string'("__________________________________")); writeLine(LogFile,logFileLine); for outrLoopVar in 2 to 2 loop LFSRVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop LFSRVar.all(loopVar) := '1'; end loop; SeedVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop SeedVar.all(loopVar) := '1'; end loop; for loopVar in 1 to (2**LFSRVar'length)+2 loop --write(logFileLine, "LFSR Value : " & to_string(LFSRVar.all)); --writeLine(LogFile,logFileLine); LFSRVar.all := lfsr(LFSRVar.all); if (LFSRVar.all = SeedVar.all and loopVar < (2**LFSRVar.all'length)-1 and loopVar /= 1) then write(logFileLine, to_string(LFSRVar.all'length) & " " & "No " & to_string(loopVar)); writeLine(LogFile,logFileLine); exit; elsif (LFSRVar.all = SeedVar.all) then write(logFileLine, to_string(LFSRVar.all'length) & " " & "Yes " & to_string(loopVar)); writeLine(LogFile,logFileLine); exit; end if; end loop; deallocate(LFSRVar); deallocate(SeedVar); end loop; file_close(LogFile); wait; end process; --function lfsr_cft(timeStrVal : string; -- freqStrVal : string) return std_logic_vector; -- returns the value that the LFSR will contain after the amount of time specified using the frequency (or period) value passed as a reference and the seed value passed as a starting point lfsr_cft_test : process constant OUTPUT_FILE : string := LOG_PATH & "lfsr_cft_test_logfile" & LOG_EXT; variable LogFileLine : line; --file LogFile : text;-- open write_mode is OUTPUT_FILE; constant timeVar : string := "17 ns"; constant freqVar : string := "1 GHz"; variable LFSRVar : std_logic_vector(lfsr_cfth(timeVar,freqVar) downto 0); variable LFSRCompleteVar : std_logic_vector(LFSRVar'range); variable LFSRCountTime : time; variable LFSRCount : integer; variable LFSRCountPeriod : time; begin LFSRCompleteVar := lfsr_cft_piped(timeVar,freqVar); LFSRCountTime := 0 ns; LFSRCount := 0; LFSRCountPeriod := to_period(1 GHz); LFSRVar := (others => '1'); for loopVar in 1 to 25 loop if (LFSRVar = LFSRCompleteVar and LFSRCountTime /= 15 ns) then assert FALSE report "lfsr_cft_test error " & LF & timeVar & " : expected" & LF & to_string(LFSRCountTime) & " : actual" severity error; end if; LFSRVar := lfsr(LFSRVar); LFSRCountTime := LFSRCountTime + LFSRCountPeriod; LFSRCount := LFSRCount + 1; end loop; wait; end process; extension_pack_lfsr_constants_generator : process constant PACKAGE_NAME : string := "extension_pack_lfsr_constants"; constant CONSTANT_NAME : string := "lfsr_constants"; constant OUTPUT_FILE : string := SRC_PATH & PACKAGE_NAME & SRC_EXT; constant LowerBound : natural := LFSRLowerBound; -- lower vector width to generate the LFSR constants for (minimum of 2) constant UpperBound : natural := LFSRUpperBound; -- upper vector width to generate the LFSR constants for variable fileStatusVar : file_open_status := open_ok; variable LogFileLine : line; file LogFile : text; --open write_mode is OUTPUT_FILE; type LFSRAccessType is access std_logic_vector; type SeedAccessType is access std_logic_vector; variable LFSRVar : LFSRAccessType; variable SeedVar : SeedAccessType; variable LFSRTestVar : std_logic_vector(7 downto 0); begin file_open(fileStatusVar, LogFile, OUTPUT_FILE, write_mode); if (fileStatusVar = open_ok) then write(logFileLine, string'("library ieee;")); writeLine(LogFile,logFileLine); write(logFileLine, "use ieee.std_logic_1164.all;" & LF); writeLine(LogFile,logFileLine); write(logFileLine, "package " & PACKAGE_NAME & " is" & LF); writeLine(LogFile,logFileLine); for outrLoopVar in LowerBound to UpperBound loop LFSRVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop LFSRVar.all(loopVar) := '1'; end loop; SeedVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop SeedVar.all(loopVar) := '1'; end loop; write(logFileLine, "type " & CONSTANT_NAME & "_type" & to_string(outrLoopVar) & " is array(1 to " & to_string(2**outrLoopVar-1) & ") of std_logic_vector(" & to_string(LFSRVar.all'high) & " downto " & to_string(LFSRVar.all'low) & ");"); writeLine(LogFile,logFileLine); write(logFileLine, "constant " & CONSTANT_NAME & to_string(outrLoopVar) & " : " & CONSTANT_NAME & "_type" & to_string(outrLoopVar) &" :=("); writeLine(LogFile,logFileLine); for loopVar in 1 to (2**LFSRVar'length)+2 loop write(logFileLine, """" & to_string(LFSRVar.all) & """"); if (loopVar = (2**LFSRVar'length)-1) then write(logFileLine, ");" & LF); else write(logFileLine, string'(",")); end if; writeLine(LogFile,logFileLine); LFSRVar.all := lfsr(LFSRVar.all); if (LFSRVar.all = SeedVar.all and loopVar < (2**LFSRVar.all'length)-1 and loopVar /= 1) then exit; elsif (LFSRVar.all = SeedVar.all) then exit; end if; end loop; deallocate(LFSRVar); deallocate(SeedVar); end loop; write(logFileLine, string'("attribute lfsrArrayLength : integer;")); writeLine(LogFile,logFileLine); for loopVar in LowerBound to UpperBound loop write(logFileLine, "attribute lfsrArrayLength of " & CONSTANT_NAME & to_string(loopVar) & " : constant is " & to_string(loopVar) & ";"); writeLine(LogFile,logFileLine); end loop; write(logFileLine, LF & string'("type LFSRRecType is record")); writeLine(LogFile,logFileLine); for loopVar in LowerBound to UpperBound loop write(logFileLine, " \" & to_string(loopVar) & "\ : " & CONSTANT_NAME & "_type" & to_string(loopVar) & ";"); writeLine(LogFile,logFileLine); end loop; write(logFileLine, string'("end record LFSRRecType;") & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("constant lfsrRec : LFSRRecType :=(")); writeLine(LogFile,logFileLine); for loopVar in LowerBound to UpperBound loop write(logFileLine, CONSTANT_NAME & to_string(loopVar)); if (loopVar = UpperBound) then write(logFileLine, string'(");") & LF); else write(logFileLine, string'(",")); end if; writeLine(LogFile,logFileLine); end loop; write(logFileLine, string'("end " & PACKAGE_NAME & ";") & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("package body " & PACKAGE_NAME & " is")); writeLine(LogFile,logFileLine); write(logFileLine, string'("end " & PACKAGE_NAME & ";")); writeLine(LogFile,logFileLine); file_close(LogFile); elsif (fileStatusVar = status_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = status_error" & LF severity error; elsif (fileStatusVar = name_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = name_error" & LF severity error; elsif (fileStatusVar = mode_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = mode_error" & LF severity error; end if; wait; end process; extension_pack_lfsr_str_generator : process type LFSRAccessType is access std_logic_vector; type SeedAccessType is access std_logic_vector; file LogFile : text; --open write_mode is OUTPUT_FILE; constant PACKAGE_NAME : string := "extension_pack_lfsr_str_constants"; constant CONSTANT_NAME : string := "lfsr_str"; constant OUTPUT_FILE : string := SRC_PATH & PACKAGE_NAME & SRC_EXT; constant LowerBound : natural := LFSRLowerBound; -- lower vector width to generate the LFSR constants for (minimum of 2) constant UpperBound : natural := LFSRUpperBound; -- upper vector width to generate the LFSR constants for variable arrayDepth : integer := 0; variable fileStatusVar : file_open_status := open_ok; variable LFSRTestVar : std_logic_vector(7 downto 0); variable LFSRVar : LFSRAccessType; variable LogFileLine : line; variable SeedVar : SeedAccessType; begin file_open(fileStatusVar, LogFile, OUTPUT_FILE, write_mode); if (fileStatusVar = open_ok) then for loopVar in LowerBound to UpperBound loop arrayDepth := 2**loopVar-1 + arrayDepth; end loop; write(logFileLine, string'("library ieee;")); writeLine(LogFile,logFileLine); write(logFileLine, "use ieee.std_logic_1164.all;" & LF); writeLine(LogFile,logFileLine); write(logFileLine, "package " & PACKAGE_NAME & " is" & LF); writeLine(LogFile,logFileLine); write(logFileLine, "type " & CONSTANT_NAME & "_type" & " is array(1 to " & to_string(arrayDepth) & ") of string(1" & " to " & to_string(UpperBound) & ");"); writeLine(LogFile,logFileLine); write(logFileLine, "constant " & CONSTANT_NAME & " : " & CONSTANT_NAME & "_type :=("); writeLine(LogFile,logFileLine); for outrLoopVar in LowerBound to UpperBound loop LFSRVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop LFSRVar.all(loopVar) := '1'; end loop; SeedVar := new std_logic_vector(outrLoopVar-1 downto 0); for loopVar in outrLoopVar-1 downto 0 loop SeedVar.all(loopVar) := '1'; end loop; for loopVar in 1 to (2**LFSRVar'length)-1 loop write(logFileLine, " " & """" & ext(to_string(LFSRVar.all),UpperBound) & """"); if (outrLoopVar = UpperBound and loopVar = (2**LFSRVar'length)-1) then write(logFileLine, string'(");") & LF); else write(logFileLine, string'(",")); end if; writeLine(LogFile,logFileLine); LFSRVar.all := lfsr(LFSRVar.all); if (LFSRVar.all = SeedVar.all and loopVar < (2**LFSRVar.all'length)-1 and loopVar /= 1) then exit; elsif (LFSRVar.all = SeedVar.all) then exit; end if; end loop; deallocate(LFSRVar); deallocate(SeedVar); end loop; writeLine(LogFile,logFileLine); write(logFileLine, string'("attribute lfsr_str_length_low : integer;")); writeLine(LogFile,logFileLine); write(logFileLine, "attribute lfsr_str_length_low of " & CONSTANT_NAME & " : constant is " & to_string(LowerBound) & ";" & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("attribute lfsr_str_length_high : integer;")); writeLine(LogFile,logFileLine); write(logFileLine, "attribute lfsr_str_length_high of " & CONSTANT_NAME & " : constant is " & to_string(UpperBound) & ";" & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("end " & PACKAGE_NAME & ";") & LF); writeLine(LogFile,logFileLine); write(logFileLine, string'("package body " & PACKAGE_NAME & " is")); writeLine(LogFile,logFileLine); write(logFileLine, string'("end " & PACKAGE_NAME & ";")); writeLine(LogFile,logFileLine); file_close(LogFile); elsif (fileStatusVar = status_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = status_error" & LF severity error; elsif (fileStatusVar = name_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = name_error" & LF severity error; elsif (fileStatusVar = mode_error) then assert FALSE report PACKAGE_NAME & LF & "fileStatusVar = mode_error" & LF severity error; end if; wait; end process; --function mult_s(Multiplier : std_logic_vector; -- Multiplicand : std_logic_vector) return std_logic_vector; -- signed multiply signed_mult_test : process begin assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 1 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 2 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("000","011") = "000000") -- 0 report "mult_s error # 3 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("000","011")) & " : actual" severity error; assert (mult_s("011","000") = "000000") -- 0 report "mult_s error # 4 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("011","000")) & " : actual" severity error; assert (mult_s("000","101") = "000000") -- 0 report "mult_s error # 5 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("000","101")) & " : actual" severity error; assert (mult_s("101","000") = "000000") -- 0 report "mult_s error # 6 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_s("101","000")) & " : actual" severity error; assert (mult_s("011","101") = "110111") -- 3 * (-3) = -9 report "mult_s error # 7 " & LF & to_string("110111") & " : expected" & LF & to_string(mult_s("011","101")) & " : actual" severity error; assert (mult_s("011","100") = "110100") -- 3 * (-4) = -12 report "mult_s error # 8 " & LF & to_string("110100") & " : expected" & LF & to_string(mult_s("011","100")) & " : actual" severity error; assert (mult_s("101","101") = "001001") -- (-3) * (-3) = 9 report "mult_s error # 9 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("101","101")) & " : actual" severity error; assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 10 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("011","011") = "001001") -- 0 report "mult_s error # 11 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_s("100","100") = "010000") -- -4 * -4 = 16 report "mult_s error # 11 " & LF & to_string("010000") & " : expected" & LF & to_string(mult_s("100","100")) & " : actual" severity error; wait; end process; --function mult_us(Multiplier : std_logic_vector; -- Multiplicand : std_logic_vector) return std_logic_vector; -- unsigned multiply unsigned_mult_test : process begin assert (mult_us("011","011") = "001001") -- 0 report "mult error # 1 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_s("011","011")) & " : actual" severity error; assert (mult_us("011","011") = "001001") -- 0 report "mult error # 2 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_us("011","011")) & " : actual" severity error; assert (mult_us("000","011") = "000000") -- 0 report "mult error # 3 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("000","011")) & " : actual" severity error; assert (mult_us("011","000") = "000000") -- 0 report "mult error # 4 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("011","000")) & " : actual" severity error; assert (mult_us("000","101") = "000000") -- 0 report "mult error # 5 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("000","101")) & " : actual" severity error; assert (mult_us("101","000") = "000000") -- 0 report "mult error # 6 " & LF & to_string("000000") & " : expected" & LF & to_string(mult_us("101","000")) & " : actual" severity error; assert (mult_us("011","011") = "001001") -- 0 report "mult error # 7 " & LF & to_string("001001") & " : expected" & LF & to_string(mult_us("011","011")) & " : actual" severity error; wait; end process; --function nat_to_slv(natVal : natural) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the natural value passed --function neg(VectorVal : std_logic_vector) return std_logic_vector; -- returns the negated value --function now return string; -- returns a string representation of the current simulation time now_test : process begin wait for 3 sec; assert (now = time'image(now)) report "now_test error # 1 " & LF & time'image(now) & " : expected" & LF & now & " : actual" severity error; wait; end process; --function reduce(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed reduce_test : process begin assert (reduce("00000") = "00") -- 0 report "reduce error # 1 " & LF & to_string("11") & " : expected" & LF & to_string(reduce("00000")) & " : actual" severity error; assert (reduce("00001") = "01") -- 1 report "reduce error # 2 " & LF & "expected : " & to_string("01") & LF & "actual : " & to_string(reduce("00001")) severity error; assert (reduce("11111") = "11") -- -1 report "reduce error # 3 " & LF & "expected : " & to_string("11") & LF & "actual : " & to_string(reduce("11111")) severity error; assert (reduce("10000") = "10000") -- -16 report "reduce error # 4 " & LF & "expected : " & to_string("10000") & LF & "actual : " & to_string(reduce("10000")) severity error; wait; end process; --function reduce_high(vectorVal : std_logic_vector) return integer; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed --function reduce_high_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'high value of a vector just large enough to represent the standard logic vector value passed --function reduce_length(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed (including a sign bit) --function reduce_length_unsigned(vectorVal : std_logic_vector) return integer; -- returns an integer value that represents the vector'length value of a vector just large enough to represent the standard logic vector value passed --function reduce_unsigned(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the standard logic vector value passed --function seq(str1Val : string; -- str2Val : string) return boolean; --function shl(vectorVal : std_logic_vector; -- natVal : natural) return std_logic_vector; --function slv_to_bcd(vectorVal : std_logic_vector; -- BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified --function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed --function slv_to_bcd_pipe(BCD_RVal : std_logic_vector; -- MSB_Val : std_logic; -- BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value --function str_to_int(stringVal : string) return integer; -- converts an Integer string to an integer str_to_int_test : process variable intVar : integer; begin intVar := str_to_int("10"); -- 3210 assert (intVar = 10) report "str_to_int_test error # 1 " & LF & "expected : 10" & LF & "actual : " & to_string(intVar) severity error; intVar := str_to_int("E-10 sec"); -- 3210 assert (intVar = -10) report "str_to_int_test error # 2 " & LF & "expected : -10" & LF & "actual : " & to_string(intVar) severity error; intVar := str_to_int("E-6 sec"); -- 3210 assert (intVar = -6) report "str_to_int_test error # 3 " & LF & "expected : -6" & LF & "actual : " & to_string(intVar) severity error; wait; end process; --function str_to_led(stringVal : string; -- CAVal : boolean) return std_logic_vector; -- converts a Hexadecimal string of any length to a std_logic_vector for seven segment LEDs --function strval_to_slv(stringVal : string) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector strval_to_slv_test : process begin assert (strval_to_slv("1") = "01") -- 0 report "bcd_to_led_test error # 1 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1")) & " : actual" severity error; assert (strval_to_slv("0") = "0") -- 0 report "bcd_to_led_test error # 1 " & LF & to_string("00") & " : expected" & LF & to_string(strval_to_slv("0")) & " : actual" severity error; assert (strval_to_slv("-1") = "11") -- -1 report "bcd_to_led_test error # 1 " & LF & to_string("11") & " : expected" & LF & to_string(strval_to_slv("-1")) & " : actual" severity error; assert (strval_to_slv("10 us") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 1 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv("10 us")) severity error; assert (strval_to_slv(" 10 us") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 2 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10 us")) severity error; assert (strval_to_slv(" 10 us ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 3 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10 us ")) severity error; assert (strval_to_slv(" 10.0 us ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 4 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10.0 us ")) severity error; assert (strval_to_slv(" 0.0100 ms ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 5 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.0100 ms ")) severity error; assert (strval_to_slv(" 0.0000100sec ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 6 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.0000100sec ")) severity error; assert (strval_to_slv(" 10E-6 sec ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 6a " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10E-6 sec ")) severity error; assert (strval_to_slv(" 10,000,000,000 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 7 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10,000,000,000 ")) severity error; assert (strval_to_slv(" 100,000Hz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 8 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100,000Hz ")) severity error; assert (strval_to_slv(" 100kHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 9 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100kHz ")) severity error; assert (strval_to_slv(" 0.1MHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 9a " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.1MHz ")) severity error; assert (strval_to_slv(" .1 MHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 9b " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" .1 MHz ")) severity error; assert (strval_to_slv(" 0.0001GHz ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 10 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 0.0001GHz ")) severity error; assert (strval_to_slv(" 10E 9 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 11 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10E 9 ")) severity error; assert (strval_to_slv(" 10E+9 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 12 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10E+9 ")) severity error; assert (strval_to_slv(" 10.0000000E+9 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 13 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10.0000000E+9 ")) severity error; assert (strval_to_slv(" 10.0000000E+9.000 ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 13b " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 10.0000000E+9.000 ")) severity error; assert (strval_to_slv(" 100E+3 HZ") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 14 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ")) severity error; assert (strval_to_slv(" 1") = "01") report "strval_to_slv_test error # 15a " & LF & "expected : " & to_string("01") & LF & "actual : " & to_string(strval_to_slv(" 1")) severity error; assert (strval_to_slv(" -1") = "11") report "strval_to_slv_test error # 15b " & LF & "expected : " & to_string("11") & LF & "actual : " & to_string(strval_to_slv(" -1")) severity error; assert (strval_to_slv("1") = "01") report "strval_to_slv_test error # 16 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1")) & " : actual" severity error; assert (strval_to_slv("10") = "01010") report "strval_to_slv_test error # 17 " & LF & to_string("01010") & " : expected" & LF & to_string(strval_to_slv("10")) & " : actual" severity error; assert (strval_to_slv(" 100E+3 HZ ps ns MHz") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 18 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ")) severity error; assert (strval_to_slv(" 100E+3 HZ Hz") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 19 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ")) severity error; assert (strval_to_slv(" 100,000 HZ 234sec") = "01001010100000010111110010000000000") report "strval_to_slv_test error # 20 " & LF & "expected : " & to_string("01001010100000010111110010000000000") & LF & "actual : " & to_string(strval_to_slv(" 100E+3 HZ 234sec")) severity error; assert (strval_to_slv("1 day") = "0100101011110000101001110110001110111011000111000 0000000000000000000") -- 0 report "strval_to_slv_test error # 21 " & LF & to_string("010010101111000010100111011000111011101 10001110000000000000000000000") & " : expected" & LF & to_string(strval_to_slv("1 day")) & " : actual" severity error; assert (strval_to_slv("1 hr") = "0110001111101011100010011101101001001110110100000 00000000000000") -- 0 report "strval_to_slv_test error # 22 " & LF & to_string("011000111110101110001001110110100100111 011010000000000000000000") & " : expected" & LF & to_string(strval_to_slv("1 hr")) & " : actual" severity error; assert (strval_to_slv("1 min") = "0110101010010100110101110100111101000011000000000 00000000") -- 0 report "strval_to_slv_test error # 23 " & LF & to_string("011010101001010011010111010011110100001 100000000000000000") & " : expected" & LF & to_string(strval_to_slv("1 min")) & " : actual" severity error; assert (strval_to_slv("1 sec") = "0111000110101111110101001001100011010000000000000 00") -- 0 report "strval_to_slv_test error # 24 " & LF & to_string("011100011010111111010100100110001101000 000000000000") & " : expected" & LF & to_string(strval_to_slv("1 sec")) & " : actual" severity error; assert (strval_to_slv("1 ms") = "01110100011010100101001010001000000000000") -- 0 report "strval_to_slv_test error # 25 " & LF & to_string("011101000110101001010010100010000000000 00") & " : expected" & LF & to_string(strval_to_slv("1 ms")) & " : actual" severity error; assert (strval_to_slv("1 us") = "0111011100110101100101000000000") -- 0 report "strval_to_slv_test error # 26 " & LF & to_string("0111011100110101100101000000000") & " : expected" & LF & to_string(strval_to_slv("1 us")) & " : actual" severity error; assert (strval_to_slv("1 ns") = "011110100001001000000") -- 0 report "strval_to_slv_test error # 27 " & LF & to_string("011110100001001000000") & " : expected" & LF & to_string(strval_to_slv("1 ns")) & " : actual" severity error; assert (strval_to_slv("1 ps") = "01111101000") -- 0 report "strval_to_slv_test error # 28 " & LF & to_string("01111101000") & " : expected" & LF & to_string(strval_to_slv("1 ps")) & " : actual" severity error; assert (strval_to_slv("1 fs") = "01") -- 0 report "strval_to_slv_test error # 29 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1 fs")) & " : actual" severity error; assert (strval_to_slv("1 as",-24) = "011110100001001000000") -- 0 report "strval_to_slv_test error # 30 " & LF & to_string("011110100001001000000") & " : expected" & LF & to_string(strval_to_slv("1 as",-24)) & " : actual" severity error; assert (strval_to_slv("1 zs",-24) = "01111101000") -- 0 report "strval_to_slv_test error # 31 " & LF & to_string("01111101000") & " : expected" & LF & to_string(strval_to_slv("1 zs",-24)) & " : actual" severity error; assert (strval_to_slv("1 ys",-24) = "01") -- 0 report "strval_to_slv_test error # 32 " & LF & to_string("01") & " : expected" & LF & to_string(strval_to_slv("1 ys",-24)) & " : actual" severity error; assert (strval_to_slv("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs") = "0100111000011101100011110011001111110010110011000 0111010000000101001") -- 0 report "strval_to_slv_test error # 33 " & LF & to_string("010011100001110110001111001100111111001 01100110000111010000000101001") & " : expected" & LF & to_string(strval_to_slv("1 day 1 hr 1 min 1 sec 1 ms 1 us 1 ns 1 ps 1 fs")) & " : actual" severity error; wait; end process; --function strval_to_slv_high(stringVal : string) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed --function strval_to_slv_var_base(stringVal : string; -- intVal : integer) return std_logic_vector; -- converts an Integer, in string form, of any length to a std_logic_vector using the time base passed --function strval_to_slv_var_base_high(stringVal : string; -- intVal : integer) return integer; -- returns an integer representing the length of a vector needed to represent the intever value (in string form) passed using the timebase value --function strh(stringVal : string) return integer; sxt_test : process constant slvVar : std_logic_vector := "0111"; variable slv1Var : std_logic_vector(11 downto 0); variable slv2Var : std_logic_vector(11 downto 0); variable slv3Var : std_logic_vector(slv1Var'range); begin slv1Var := sxt2(int_to_slv(-1000),slv1Var'length); slv2Var := sxt2(int_to_slv(-6),slv2Var'length); assert (sxt2(slvVar,7) = "0000111") -- 7 bits report "sxt2_test error # 1 " & LF & to_string("0000111") & " : expected" & LF & to_string(sxt2(slvVar,7)) & " : actual" severity error; assert (sxt2(slvVar,4) = "0111") -- 4 bits report "sxt2_test error # 2 " & LF & to_string("0000111") & " : expected" & LF & to_string(sxt2(slvVar,4)) & " : actual" severity error; assert (sxt2("1001",7) = "1111001") -- 7 bits report "sxt2_test error # 3 " & LF & to_string("1111001") & " : expected" & LF & to_string(sxt2("1001",7)) & " : actual" severity error; assert (sxt2("00",7) = "0000000") -- 4 bits report "sxt2_test error # 4 " & LF & to_string("0000000") & " : expected" & LF & to_string(sxt2("00",7)) & " : actual" severity error; assert (sxt2("1001",4) = "1001") -- 7 bits report "sxt2_test error # 5 " & LF & to_string("1001") & " : expected" & LF & to_string(sxt2("1001",7)) & " : actual" severity error; wait; end process; --function to_int(vectorVal : std_logic_vector) return integer; -- repackaging of "conv_integer" function --function to_period(freqVal : frequency) return time; -- returns a one cycle period value for a given frequency --function to_string(intVal : integer) return string; -- returns a string value for an integer value passed to_string_test1 : process begin assert (to_string(2147000000) = "2147000000") report "to_string_test1 error # 1 " & LF & "2147000000" & " : expected" & LF & to_string(2147000000) & " : actual" severity error; assert (to_string(-2147000000) = "-2147000000") report "to_string_test1 error # 2 " & LF & "-2147000000" & " : expected" & LF & to_string(-2147000000) & " : actual" severity error; wait; end process; --function to_string(realVal : real) return string; -- returns a string value for an real value passed to_string_test2 : process begin assert (to_string(1.000000e+30 = "1.000000e+308")report "to_string_test2 error # 1 " & LF & "1.000000e+308" & " : expected" & LF & to_string(1.000000e+30 & " : actual"severity error; assert (to_string(1.000000e-30 = "1.000000e-308")report "to_string_test2 error # 2 " & LF & "1.000000e-308" & " : expected" & LF & to_string(1.000000e-30 & " : actual"severity error; assert (to_string(-1.000000e-30 = "-1.000000e-308")report "to_string_test2 error # 3 " & LF & "-1.000000e-308" & " : expected" & LF & to_string(-1.000000e-30 & " : actual"severity error; wait; end process; --function to_string(timeVal : time) return string; to_string_test3 : process begin assert (to_string(3 ns) = "3 ns") report "to_string_test3 error # 1 " & LF & "3 ns" & " : expected" & LF & to_string(3 ns) & " : actual" severity error; assert (to_string(2040 ns) = "2040 ns") report "to_string_test3 error # 2 " & LF & "2040 ns" & " : expected" & LF & to_string(2040 ns) & " : actual" severity error; wait; end process; --function to_string(vectorVal : std_logic_vector) return string; --function vhfi(intVal : integer) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the integer value passed. This assumes the rest of the range declaration of the vector will be "downto 0" --function vhfn(natVal : natural) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the natural value passed. This assumes the rest of the range declaration of the vector will be "downto 0" --function vlfi(intVal : integer) return natural; -- returns an integer representing the length of a vector needed to represent the integer value passed --function vlfn(natVal : natural) return natural; -- returns an integer representing the length of a vector needed to represent the natural value passed --function vrfi(intVal : integer) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the integer value passed --function vrfn(natVal : natural) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the natural value passed -------------------------------------------------------------------------------- ---- Procedure Declarations -------------------------------------------------------------------------------- -- --procedure clkgen( -- constant clkFreqSig : in frequency; -- signal clkSig : out std_logic); -- --procedure clkgen( -- signal clkEnSig : in boolean; -- signal clkFreqSig : in frequency; -- signal clkSig : out std_logic); -- --procedure clkgen( -- signal clkEnSig : in boolean; -- signal clkPeriodSig : in time; -- constant clkDutySig : in real; -- signal clkResetSig : in boolean; -- signal clkSig : inout std_logic); -- --procedure clkgen( -- signal clkEnSig : in boolean; -- signal clkFreqSig : in frequency; -- constant clkDutySig : in real; -- signal clkResetSig : in boolean; -- signal clkSig : inout std_logic); -- -- --procedure FF( -- signal Clk : in std_logic; -- signal Rst : in std_logic; -- signal D : in std_logic_vector; -- signal Q : out std_logic_vector); -- --procedure slv_to_bcd( -- signal BCD_RIn : in std_logic_vector; -- signal BinIn : in std_logic_vector; -- signal BinFBIn : in std_logic_vector; -- signal ClkIn : in std_logic; -- constant BCD_DigitsVal : in integer; -- signal EnIn : in std_logic; -- signal RstLowIn : in std_logic; -- signal BCD_ROut : out std_logic_vector; -- signal Bin_ROut : out std_logic_vector; -- signal DoneOut : out std_logic); --exp_test : process --variable timeBaseVar : std_logic_vector(500 downto 0); --variable lineVar : line; --begin -- timeBaseVar := ext("01",timeBaseVar'length); -- for loopVar in 1 to 50 loop -- timeBaseVar := timeBaseVar(timeBaseVar'high-4 downto 0) * "1010"; -- ---- write(lineVar,to_string(real(reduce_high(timeBaseV ar))/real(loopVar))); ---- write(lineVar,LF); -- assert FALSE -- report -- to_string(real(reduce_high(timeBaseVar))/real(loopVar)) & LF -- severity note; -- end loop; -- -- wait; --end process; --assert FALSE --report "THIS IS THE END OF SIMULATION" & LF --severity failure; ------------------------------------------------------------------------------ end behavioral; ------------------------------------------------------------------------------ -- end of extension_pack testbench -- synopsys translate_on |
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