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I already have a system in place in Verilog, and now I'm trying to get
everything ported smoothly to VHDL and am having some difficulty. Of
course, perhaps my Verilog setup isn't smooth either.

I have a test bench that I want to simulate higher level function calls
down to my design. For instance, within my test bench, I have a DUT
connected, clocks generate, resets, etc, but I also have a process that
makes calls like:

process
begin
-- SendValue(address, value)
SendValue(x"00", x"1234");

-- UpdateValue;
UpdateValue;

....

wait;
end process;

SendValue(...) and UpdateValue are procedure calls, but they are also
designed to look and function similar to function calls one of our
customers would make on a PC in C++, Python, Java, etc. On the PC, our
API's and hardware/firmware make the connection to the FPGA world. In
the simulation world, I need some behavioral procedures and functions to
make the connection.

Anyway, in Verilog, I was able to seperate a large list of functions and
tasks into a Call.v file, that is then included at the bottom of the
test bench with an `include "Call.v" directive. The functions and tasks
in Call.v are included at compile time at this point. Not perfect, but
it works. The functions and tasks in Call.v are able to utilize global
signals like the clocks, resets, data busses, etc. in the test bench
that aren't explicitly passed.

However, in VHDL, it would be nice to put all my functions and
procedures into a package. Unfortunatly, I can't get global access back
and forth between this package and my other signals. I also don't want
to spam the test bench, which is otherwise quite clean with hundreds of
lines of procedures and functions.

Any suggestions on how to organize this?

Thanks,
Garrick