In behavioural, you can (sometimes) omit clocks etc.
There are other descriptions:
structural - a (description of a) digital circuit connecting
components using (signal) wires
gate-level - structural, but using logic elements from a vendor
library as components
register-transfer-level: using processes mostly with clk/reset can
be synthesized, glitch-resistent
...
a gate-level VHDL description can be the result of a synthesis tool,
which is fed by a register-transfer-level description.
A behavioural description (aka behaviour model) can normally not be
synthesized to a gate-level "netlist".
In VHDL, at the lowest level (inside the components), there are always
processes (all concurrent statements can be replaced to equivalent to
process descriptions, the language reference manual describes how to do
this).
Hubble.
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