Intialization

Hi,
I am trying to write to a RAM. I have a 19-bit counter and one state
machine. First,I want to reset the counter and state machine at the
powerup of the FPGA. Second, when the counter reaches upto its maximum
value, I want to Reset it again and also wants to intialize the state
machine and wait for the new data from USB_Data bus.The problem is that
my counter sometimes reset at the powerup and sometimes do not reset
itself
and it also sometimes does reset itself after it reaches to its
maximum value and sometimes it does not reset itself. I tried to add
the asynchronous RESET but it does not work. Please advice. I am also
attaching the code.

Thanks
John


Entity DPR is

port (

Data_Bus ut unsigned (13 downto 0 );
Address_bus : inout unsigned (18 downto 0 );
Read_write: out std_logic;
Output_Enable : out std_logic;
DPR_CLK : in std_logic;
CE0: out std_logic;
CE1 ut std_logic;
LBL ut std_logic;
UBL out std_logic;
USB_Data :in unsigned (7 downto 0 );
USB_CLK :in std_logic;
output_signal : out std_logic;
ZZL: out std_logic:='0';
SEML: out std_logic:='1';
OPTL : in std_logic;
Async_RESET: in std_logic
);

End DPR;

Architecture DPR_ARCH of DPR IS

signal State2: unsigned(1 downto 0);
signal nextstate2: unsigned(1 downto 0);

constant G0 : unsigned(1 downto 0):="00";
constant G1 unsigned(1 downto 0):="01";
constant G2 : unsigned(1 downto 0):="10";
constant G3 : unsigned(1 downto 0):="11";

Signal inc: std_logic;
Signal Reset_A: std_logic;
Signal State1,nextstate1: integer := 0;
Signal sec_stop: std_logic;
Signal sec_counter: unsigned ( 18 downto 0);

Begin

output_signal <= sec_stop;
CE0 <= '0';
CE1 <= '1';
Output_Enable <= '1';
Read_write <= '0';
Address_bus <= sec_counter;

Process (State2 )
Begin

Case State2 is


When G0=>
inc <='0';
Data_Bus ( 13 downto <= USB_Data ( 5 downto 0 );
UBL <='0'; --1 old value
LBL <='0'; --0 0ld value

nextstate2 <=G1;

When G1 =>
inc <='0';
Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
UBL <='0'; --0 old value
LBL <='0'; --1 old value

nextstate2 <=G2;

When G2 =>
inc <='1';
Data_Bus ( 13 downto <= USB_Data ( 5 downto 0 );
UBL <='0';
LBL <='0';
nextstate2 <=G3;

When G3 =>
inc <='0';
Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
UBL <='0';
LBL <='0';

nextstate2 <=G2;
When others =>

nextstate2 <=G0;

End case;
End Process;

Process (USB_CLK ,Async_RESET)
Begin


If ( Async_RESET = '0') Then

sec_counter <= "0000000000000000000";
State2 <= G0;


Else If (USB_CLK 'Event And USB_CLK = '0') Then


State2 <= nextstate2;

If ( sec_counter (1='0' and sec_counter(17)='0' and
sec_counter(16)='0' and sec_counter(15)='0' and
sec_counter(14)='0' and sec_counter(13)='1' and
sec_counter(12)='0' and sec_counter(11)='0' and
sec_counter(10)='1' and sec_counter(9)= '0' and sec_counter(=
'0' and sec_counter(7)='0' and sec_counter (6) ='0' and
sec_counter(5)= '1' and sec_counter(4)='0' and
sec_counter(3)= '0' and sec_counter(2)= '0' and
sec_counter(1)='0' and sec_counter(0)= '0')
Then


sec_stop <= '1';
State2 <= G0;

Else
sec_stop <= '0';

End If;


If (inc = '1' AND sec_stop = '0' ) Then

sec_counter <= sec_counter + 1 ;
Else

End If;

End If;


If ( USB_CLK 'Event And USB_CLK = '0')Then

If ( sec_stop= '1' ) Then

sec_counter <= "0000000000000000000";

Else

End If;

End If;

End If;

End Process;
End DPR_ARCH;

john