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Do you still use component declarations?

 
 
Srinivasan Venkataramanan
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      09-18-2005
Hi,
My VHDL is little rusty by now. I'm thinking about direct entity
instantiation feature in VHDL-93 against lengthier component declarations.
I'm trying to see if there is still a technical need to declare components -
given that VHDL-93 has direct entity instantiation, why would you use
component declarations? I believe there is a value addition to declare
components - they can serve as sort of header files that define the
interface across blocks, but I would put that as more of a methodology than
core language. In other words: Is there any thing in the language sense that
can be done via component declaration that can't be achieved using direct
entity instantiation?

Thanks
Srini

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Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned


 
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Mike Treseler
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      09-18-2005
Srinivasan Venkataramanan wrote:

> I'm trying to see if there is still a technical need to declare components -
> given that VHDL-93 has direct entity instantiation, why would you use
> component declarations?


For me, the downside is matched component ports
as things change.

I can imagine using a comp. decl. as a placeholder for
a TBD design entity.

I see no advantage if the instance entity exists.

> Is there any thing in the language sense that
> can be done via component declaration that can't be achieved using direct
> entity instantiation?


Component configurations,
but this is poorly supported for synthesis.


-- Mike Treseler
 
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Srinivasan Venkataramanan
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      09-19-2005
Thanks Mike, yes of-ourse configuration is a big advantage when dealing with
TBs - thanks for reminding me!

Srini


 
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Colin Marquardt
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      09-19-2005
"Srinivasan Venkataramanan" <(E-Mail Removed)_spam.co.in> writes:

> I'm trying to see if there is still a technical need to declare components -
> given that VHDL-93 has direct entity instantiation, why would you use
> component declarations?


I only needed them when I was instantiating Verilog modules in VHDL
code.

Cheers,
Colin

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