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VHDL - One Signal Two Names

 
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Old 09-17-2005, 04:56 AM   #1
Default One Signal Two Names


If I have a bus --> xyz(31 downto 0) is there a way to assign another name
such that it references xyz(20 downto 10)?

Thanks,
Joel




Weddick
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Old 09-17-2005, 05:33 PM   #2
Mike Treseler
 
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Default Re: One Signal Two Names
Weddick wrote:
> If I have a bus --> xyz(31 downto 0) is there a way to assign another name
> such that it references xyz(20 downto 10)?


You could use an alias for this.
The downside is that aliases are not visible in simulation.

You could declare variables (or signals) for the fields.

variable left_v : unsigned(10 downto 0);
variable mid_v : unsigned(10 downto 0);
variable left_v : unsigned( 9 downto 0);

and use these to assign to the bus:

bus <= left_v & mid_v & left_v;

-- Mike Treseler


Mike Treseler
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Old 09-17-2005, 06:41 PM   #3
Mike Treseler
 
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Default Re: One Signal Two Names - typo
Mike Treseler wrote:

> variable left_v : unsigned( 9 downto 0);

_right_v_

> and use these to assign to the bus:
> bus <= left_v & mid_v & left_v;

_right_v_


Mike Treseler
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Old 09-18-2005, 05:09 AM   #4
Weddick
 
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Default Re: One Signal Two Names
Thanks Mike,

Looks like alias would do the trick if it would work in simulation also.

Joel


"Mike Treseler" <> wrote in message
news:...
> Weddick wrote:
>> If I have a bus --> xyz(31 downto 0) is there a way to assign another
>> name such that it references xyz(20 downto 10)?

>
> You could use an alias for this.
> The downside is that aliases are not visible in simulation.
>
> You could declare variables (or signals) for the fields.
>
> variable left_v : unsigned(10 downto 0);
> variable mid_v : unsigned(10 downto 0);
> variable left_v : unsigned( 9 downto 0);
>
> and use these to assign to the bus:
>
> bus <= left_v & mid_v & left_v;
>
> -- Mike Treseler





Weddick
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Old 09-18-2005, 06:31 PM   #5
Srinivasan Venkataramanan
 
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Default Re: One Signal Two Names
Mike,
What exactly do you mean by:
> You could use an alias for this.
> The downside is that aliases are not visible in simulation.


Since alias doesn't create new objects, tools are not able to display them
in Waveforms?

Thanks
Srini




Srinivasan Venkataramanan
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Old 09-18-2005, 07:44 PM   #6
Mike Treseler
 
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Default Re: One Signal Two Names
Srinivasan Venkataramanan wrote:

> Since alias doesn't create new objects, tools are not able to display them
> in Waveforms?


Last time I tried this in modelsim, I could see the
base variable but not the alias slice.

Declared objects are always visible in sim.

-- Mike Treseler



Mike Treseler
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