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09-15-2005, 02:12 PM
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#1 |
aclr to FIFO
Hi all,
I am using Altera IP core for a dual-clock FIFO. I want to assert the 'async clear' port of the FIFO every time it gets full. The simplest design I thought can be using the 'full' or 'almost full' as a control to select aclr. However, this creates a feedback loop from output to the input, which is probably a bad design. Is there a better way to do that? vizziee@gmail.com |
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09-15-2005, 02:27 PM
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#2 |
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Posts: n/a
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Re: aclr to FIFO
> I want to assert the 'async clear' port of the FIFO every time it gets
full. Nooooooooooooooooooooooooooooooooooooooooooooooooo oooo! Ben Jones |
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09-16-2005, 06:38 AM
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#3 |
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Posts: n/a
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Re: aclr to FIFO
Ben Jones wrote: > > I want to assert the 'async clear' port of the FIFO every time it gets > full. > > Nooooooooooooooooooooooooooooooooooooooooooooooooo oooo! Well, sooooooooooooooooooooo...I got workaround the problem. I noted that when the FIFO gets full it disables the rdreq signal. So I don't read any new data thereafter. That solves my problem. vizziee@gmail.com |
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