not

hi,

whats wrong here? is "not" together with signed/unsigned wrong?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- sutest
entity sutest is
port (
IN0 : in unsigned(31 downto 0);
OUT0 : out unsigned(31 downto 0)
);
end sutest;

architecture sutest_arch of sutest is
begin
process( IN0 )
begin
OUT0 <= (NOT IN0);
end process;
end sutest_arch;

Regards,
Hen

Hendrik Greving

As far as I can see, "not" is not part of package
ieee.std_logic_arith

You can use ieee.numeric_std instead (if your synthesis tool allows
this), which defines a not operation. Otherwise, you have to cast to
std_logic_vector

OUT0<=unsigned(NOT(std_logic_vector(INO)));

or even

OUT0<=unsigned(std_logic_vector'(NOT(std_logic_vec tor(INO))));


Hubble.

Hubble