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VHDL - generate statement

 
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Old 09-11-2005, 12:52 PM   #1
Default generate statement


I need to represent the following in a generate statement

p(1) = y(0) * c(1)
p(3) = y(1) * c(3)
p(5) = y(2) * c(5)
p(i) = y(i-n) * c(i)
and so on...

I basically need to use two indices. How can I do this?

Thanks



crazyrdx
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Old 09-11-2005, 03:11 PM   #2
Ralf Hildebrandt
 
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Default Re: generate statement
crazyrdx wrote:
> I need to represent the following in a generate statement
>
> p(1) = y(0) * c(1)
> p(3) = y(1) * c(3)
> p(5) = y(2) * c(5)
> p(i) = y(i-n) * c(i)
> and so on...
>
> I basically need to use two indices. How can I do this?


What about two for-generate outside (and nested) for the indices and
finally an if generate?

Ralf


Ralf Hildebrandt
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