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VHDL - [XST] ise6.3i finds FSM and ISE7.1 doesn't, why?

 
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Old 09-10-2005, 07:01 PM   #1
Default [XST] ise6.3i finds FSM and ISE7.1 doesn't, why?


Hey,

I made a FSM with about 23 states (not the first time i've done vhdl
work, but never had this problem before with FSM => in fact it is not
really a problem) and i used following scheme:

sequencingrocess(state,...)
begin
case state is
when ... =>
end case;
end process;

updaterocess(reset, clk)
begin
if (reset='1') then
state<=...;
elsif (clk'event and clk='1') then
state<=next_state;
end if;
end process;

logicrocess(clk)
begin
if (clk'event and clk='1') then
...
end if;
end process;

so i don't think it is the way the fsm is build up ... so when i
compile it it does say :

Using one-hot encoding for signal <state>.

but i don't get a f.e.

Found finite state machine <FSM_0> for signal <state>.

-----------------------------------------------------------------------
| States | 3
|
| Transitions | 7
|
| Inputs | 4
|
| Outputs | 3
|
| Clock | clk (rising_edge)
|
| Reset | reset (positive)
|
| Reset type | asynchronous
|
| Reset State | idle
|
| Power Up State | idle
|
| Encoding | automatic
|
| Implementation | LUT
|

-----------------------------------------------------------------------

oh, and i forgot to mention that it found the FSM in ISE6.1 but not in
ISE7.1 ...

the result:

Found finite state machine <FSM_0> for signal <state>.

-----------------------------------------------------------------------
| States | 23
|
| Transitions | 82
|
| Inputs | 38
|
| Outputs | 28
|
| Clock | clk (rising_edge)
|
| Reset | reset (positive)
|
| Reset type | asynchronous
|
| Reset State | idle_st
|
| Power Up State | idle_st
|
| Encoding | automatic
|
| Implementation | LUT
|

-----------------------------------------------------------------------


and i was just wondering why XST does not find my FSM????

thank you in advance,

kind regards,

Tim






Tim Verstraete
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Old 09-12-2005, 05:39 PM   #2
Mike Treseler
 
Posts: n/a
Default Re: [XST] ise6.3i finds FSM and ISE7.1 doesn't, why?
Tim Verstraete wrote:


> and i was just wondering why XST does not find my FSM????


Finding FSMs is an abstraction by XST not VHDL.
Open a case with Xilinx if you really think
it matters.

-- Mike Treseler


Mike Treseler
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