Go Back   Velocity Reviews > Newsgroups > VHDL
User Name
Password
Register FAQ Members List Calendar Search Today's Posts Mark Forums Read

Reply

VHDL - Generate simulator commands from waveform

 
Thread Tools Search this Thread
Old 09-08-2005, 01:58 PM   #1
Default Generate simulator commands from waveform


Hi,

I'm using modelsim and have a requirement of generating simulator
commands for a sequence of signals for which I have the waveforms.

Can anyone tell me how to do it ? Would appreciate any help.

Thanks,
-Anil



Anil
  Reply With Quote
Old 09-08-2005, 02:08 PM   #2
Zara
 
Posts: n/a
Default Re: Generate simulator commands from waveform
Anil wrote:
> Hi,
>
> I'm using modelsim and have a requirement of generating simulator
> commands for a sequence of signals for which I have the waveforms.
>
> Can anyone tell me how to do it ? Would appreciate any help.
>
> Thanks,
> -Anil
>


For every signal you have a waveform:

process
begin
signal<='0'; -- initial_value
wait for 347 ns; -- delay until value changes
signal <='1';
wait for 12 ns; -- delay until value changes
signal<='0';

(....)

wait; -- no more changes
end process;

For a square clock:

process
begin
clock<='0';
loop
wait for 5 ns; -- half clock period
clock<=not clock;
end loop;
end process;

Hope this is what you wanted...

Bets regards

Zara


Zara
  Reply With Quote
Old 09-09-2005, 05:28 AM   #3
Srinivasan Venkataramanan
 
Posts: n/a
Default Re: Generate simulator commands from waveform
Anil,
Can you elaborate on why would you require such a flow? I know of
many tools that can turn a VCD file to a HDL (Verilog/VHDL)
testbenches for easy replay. Also there are tools that can turn
timing diagrams to testbenches. The issue in converting them to sim
commands (as I see):

1. Sim commands are not portable across simulators
2. Inefficient - usually TCL tbs tend to be slower than HDL ones.
3. Debug - lot of us know how to debug HDL/HVL not TCL so well.

Having said all this, if you still insist to generate TCL commands, I
would recommend you to develop a PERL script to take a HDL TB
generated from a VCD and turn it to TCL. It is not that difficult.

Good Luck
Srini


--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Anil" <> wrote in message
news: ups.com...
> Hi,
>
> I'm using modelsim and have a requirement of generating simulator
> commands for a sequence of signals for which I have the waveforms.
>
> Can anyone tell me how to do it ? Would appreciate any help.
>
> Thanks,
> -Anil
>





Srinivasan Venkataramanan
  Reply With Quote
Reply


Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Generate .aspx file and .cs file behind it jyoti.bannigidad@gmail.co Software 0 09-18-2008 07:54 AM




SEO by vBSEO 3.3.2 ©2009, Crawlability, Inc.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46