Hi Toby,
> there doesnt seem to be any to_unsigned(std_logic_vector) function
> in the numeric_std library, why is that? is there any way around that?
The numeric_std "signed" and "unsigned" types are defined exactly like the
type "std_logic_vector" is defined in std_logic_1164  they are all arrays
with elements of type std_logic. This makes them what VHDL calls "related"
types, which can easily be convered between. For example:
signal x,y : std_logic_vector(7 downto 0);
signal a,b : unsigned(7 downto 0);
x <= std_logic_vector(a);
b <= unsigned(y);
Ben
