Reading internal signals through a testbench.

Hi all,
Through a testbench (Verilog or VHDL), how do I read the values of
signals of a sub module through a top module? This is required to match
and assert if the program is working correctly. Please help. Thank you.

Best Regards,

CODE_IS_BAD

CODE_IS_BAD wrote:

> Through a testbench (Verilog or VHDL), how do I read the values of
> signals of a sub module through a top module?

http://groups.google.com/groups?q=vhdl+port+spy+package

Mike Treseler

> Through a testbench (Verilog or VHDL), how do I read the values of
> signals of a sub module through a top module?
Use the 'signal spy' feature of ModelSim (but before that, check if
your version of ModelSim supports it or not).

vizziee@gmail.com