Velocity Reviews > VHDL > Finding the execution time

# Finding the execution time

a_Conan
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Posts: n/a

 09-02-2005
Hi, Suppose I have written algorithm in VHDL. This algorithm has
sequential statements before the final result appeared.
My question: can I calculate the time need on microsecond from the
first input until the last output? Like in Matlab we use "tic" in first
line and "toc" in the last line? i.e. how can I find the execution time
for my algorithm?
Thank you.

Nicolas Matringe
Guest
Posts: n/a

 09-02-2005
a_Conan wrote:
> Hi, Suppose I have written algorithm in VHDL. This algorithm has
> sequential statements before the final result appeared.
> My question: can I calculate the time need on microsecond from the
> first input until the last output? Like in Matlab we use "tic" in first
> line and "toc" in the last line? i.e. how can I find the execution time
> for my algorithm?

This depends on your clock frequency but from your question I think
that your algorithm is purely combinational (combinatorial?). Thus the
'execution' time will depend on your hardware implementation (ASIC?
FPGA?)

Nicolas

a_Conan
Guest
Posts: n/a

 09-02-2005
Hi Nicolas, yes my algorithm depends to multiple calculations separated
in functions and procedures such as:
..
..
..
for i in 1 to M loop--start from the second row
for k in 0 to (N - i) loop
Matrix_out(i, k) := Matrix_in(i, i + k);
end loop;
for k in 0 to (i - 1) loop
Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
end loop;
end loop;
..
..
..

every function can call others as need.
suppose my clock frequency is 50MHz. so how can I find the exe-time.
I will use FPGA.

Nicolas Matringe
Guest
Posts: n/a

 09-02-2005
This is quite a big arithmetic block...
Functions and procedure are to be used with great care in synthesizable
code (especially procedures).
If you don't have any synchronous process, your max speed will depend
on the FPGA (brand & family) but anyway it may well be very slow.
Remember that VHDL is definitely *not* a programming language. Always
think hardware.

Nicolas

a_Conan
Guest
Posts: n/a

 09-02-2005
Do you think I can do it like this:
..
..
T1 := NOW
function1 :=( N1 , N2)
function2 :=( N1 , N2)
function3 :=( N1 , N2)
T2 := NOW - T1;
..
..

Guest
Posts: n/a

 09-02-2005

Stop thinking software !!!

Your two loops with 2 dimensions vector cannot be synthesizable !!

I think you better use a RAM and make transfert inside the RAM...

Are you just doing simulation or you want to implant it in a FPGA

Guest
Posts: n/a

 09-02-2005

Stop thinking software !!!

Your two loops with 2 dimensions vector cannot be synthesizable !!

I think you better use a RAM and make transfert inside the RAM...

Are you just doing simulation or you want to implant it in a FPGA

a_Conan
Guest
Posts: n/a

 09-02-2005
Sorry patrick, do you mean I cannot synthesize the upper code on my
FPGA?
Are you sure?

a_Conan
Guest
Posts: n/a

 09-03-2005
Ok, Patric can you tell me how can I do
for i in 1 to M loop--start from the second row
for k in 0 to (N - i) loop
Matrix_out(i, k) := Matrix_in(i, i + k);
end loop;
for k in 0 to (i - 1) loop
Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
end loop;
end loop;

in RAM to make it synthesizable ?

Thanks

Ralf Hildebrandt
Guest
Posts: n/a

 09-03-2005
a_Conan wrote:

> Ok, Patric can you tell me how can I do
> for i in 1 to M loop--start from the second row
> for k in 0 to (N - i) loop
> Matrix_out(i, k) := Matrix_in(i, i + k);
> end loop;
> for k in 0 to (i - 1) loop
> Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
> end loop;
> end loop;
>
> in RAM to make it synthesizable ?

1st of all: Get knowledge about flipflops, combinational logic and
latches. Make yourself familiar with the concept of a state machine -
especially a synthesizable state machine in VHDL.

2nd: Think about a data path, on which such an algorithm may be
implemented. You need a state machine and inside some states you connect
some blocks (registers, arithmetic units...) together. Everything
step-by-step, controlled by a state machine.

VHDL may be used like a programming language, but only for simulation
purpose. If you want to model real hardware you have to think hardware.

Ralf