Error in clock divider from FAQ

Hello,

the clock divider from the FAQ is:

architecture Behavior of ClockDivider is
begin
process (ClkIn, Reset)
variable Count: Natural range 0 to Modulus-1;
begin
if Reset = '1' then
Count := 0;
ClkOut <= '0';
elsif ClkIn = '1' and ClkIn'event then
if Count = Modulus-1 then
Count := 0;
else
Count := Count + 1;
end if;
if Count >= Modulus/2 then
ClkOut <= '0';
else
ClkOut <= '1';
end if;
end if;
end process;
end Behavior;

In my simulation (ModelSim) the first '1' cycle of ClkOut is too short
by one ClkIn cycle.
Fixes for that:
- Initialize count with Modulus-1 in reset OR
- Count up _after_ ClkOut is set

I wonder why nobody came accross this problem. It's there quite
a long time.
I don't have information who is maintaining the FAQ and who could
fix this.

Bye,
Y

yolanda3000@freenet.de

wrote:
> Hello,
>
> the clock divider from the FAQ is:
>
> architecture Behavior of ClockDivider is
> begin
> process (ClkIn, Reset)
> variable Count: Natural range 0 to Modulus-1;
> begin
> if Reset = '1' then
> Count := 0;
> ClkOut <= '0';
> elsif ClkIn = '1' and ClkIn'event then
> if Count = Modulus-1 then
> Count := 0;
> else
> Count := Count + 1;
> end if;
> if Count >= Modulus/2 then
> ClkOut <= '0';
> else
> ClkOut <= '1';
> end if;
> end if;
> end process;
> end Behavior;
>
> In my simulation (ModelSim) the first '1' cycle of ClkOut is too short
> by one ClkIn cycle.
> Fixes for that:
> - Initialize count with Modulus-1 in reset OR
> - Count up _after_ ClkOut is set
>
> I wonder why nobody came accross this problem. It's there quite
> a long time.
> I don't have information who is maintaining the FAQ and who could
> fix this.
>
> Bye,
> Y

I just simulated the divider using Active-HDL and got the same result
that you did. You are very observant! I have used this divider a
number of time and never noticed the problem.

Charles

charles.elias@wpafb.af.mil

wrote:
> wrote:
>
>>Hello,
>>
>>the clock divider from the FAQ is:
>>
>>architecture Behavior of ClockDivider is
>> begin
>> process (ClkIn, Reset)
>> variable Count: Natural range 0 to Modulus-1;
>> begin
>> if Reset = '1' then
>> Count := 0;
>> ClkOut <= '0';
>> elsif ClkIn = '1' and ClkIn'event then
>> if Count = Modulus-1 then
>> Count := 0;
>> else
>> Count := Count + 1;
>> end if;
>> if Count >= Modulus/2 then
>> ClkOut <= '0';
>> else
>> ClkOut <= '1';
>> end if;
>> end if;
>> end process;
>> end Behavior;
>>
>>In my simulation (ModelSim) the first '1' cycle of ClkOut is too short
>>by one ClkIn cycle.
>>Fixes for that:
>>- Initialize count with Modulus-1 in reset OR
>>- Count up _after_ ClkOut is set
>>
>>I wonder why nobody came accross this problem. It's there quite
>>a long time.
>>I don't have information who is maintaining the FAQ and who could
>>fix this.
>>
>>Bye,
>>Y
>
>
> I just simulated the divider using Active-HDL and got the same result
> that you did. You are very observant! I have used this divider a
> number of time and never noticed the problem.
>
> Charles
>

The reason is pretty simple: In normal cycles, ClkOut changes from '0'
to '1' when Count changes from Modulus/2 to Modulus/2+1, and the other
way round when Count changes from '0' to '1'. So, simlutaneously with
Count=1, ClkOut='1'.

But on reset, Count is given the value '0' and ClkOut too, not
corresponding to the rest of the time.
Solutions:

a) Either initialize ClkOut on reset with the value '1'
b) Or change ths sign of both ClkOut transitions

Zara