Metastability or what?

Hi Folks!

I got a real strange problem in my virtex2 FPGA. The hole thing is an
image processing unit and the FPGA does the digital part of the image
capture.

The piece of code I have trouble is a reset of the video-input FIFO,
which is should be activated by the CPU setting the "iCnt_rst" signal.
I want to delay the reset of the FIFO for at least one line which does
the "Dly" signal and end the reset by the falling edge of the Hsync.
I would like to have it all synchron to the "iV_clk".

Most of the time the code works how it should, but sometimes I can see
a falling edge of sMan_rst, far away of any edge on sHsync (sHsync =
1). There is input-FF on sHsync, so I should see it go low for one
clock cycle if I route it to a testpoint, but it stays high!

We had some unexpected behaviour before due to glitches on clocks and
other noises, but how can this behaviour be explained?


Thanks!

Wolfgang Kopp


-------------------------------------------

pHsync_reg: process (iReset, iV_clk)
begin
if (iReset = '1') then
sHsync_reg <= sHsync;
elsif rising_edge (iV_clk) then
sHsync_reg <= sHsync;
end if;
end process;

pMan_rst: process (iReset, iV_clk)
begin
if (iReset = '1') then
sMan_rst <= '1';
Dly <= '0';
elsif rising_edge (iV_clk) then
if (iCnt_rst = '1') then
sMan_rst <= '1';
Dly <= '0';
elsif (sHsync = '0' and sHsync_reg = '1') then
if (Dly = '1') then
sMan_rst <= '0';
end if;
Dly <= '1';
end if;
end if;
end process;

woko

If you have an asynchronous signal coming into a device, you cannot use
it to compare to the registered version. You must register sHsync_reg
and compare that result:

sHsync_reg2 <= sHsync_reg;
elsif (sHsync_reg = ' 0' and sHsync_reg2 = '1') then

The problem you're having would occur is the signal changes near the
clock transition. This could cause a metastable state that would cause
both the input and regsitered version to potentially go low at the same
time without a clock delay. If you really want to avoid metastability,
double register, then register a 3rd time and use reg3 and reg2 as your
edge detector.

Enjoy,
Beanut

fourbeans@gmail.com

Here is a How-To:
http://www.interfacebus.com/Design_MetaStable.html


Home page at:
http://www.interfacebus.com/

www.interfacebus.com

I did some more investigations by measurements and I guess I found the
problem now. Metastability is not the fault here, the problem is seen
too often, around every minute.
The problem is the asynchronous input iCnt_rst. From the vhdl-code it
looks like the signal sMan_rst could not got to '0' by iCnt_rst. But
the logic can not be implemented like that. There is combinatorial
logic
with iCnt_rst for the CE of the FF which could cause unexpected
results, if the input changes at the clockedge.
If I register iCnt_rst the problem is gone.

Thanks anyway,

Wolfgang Kopp

woko