Vhdl testbench with textio package

Hello everybody !

I'm design a digital video systems based on MPEG transport Stream
(DVB).
In fact I want to create a model and I must elaborate a DVB generator.

The DVB generator play a file (with hexa values) and I want to inject
these values in a VHDL block.

data_int is STD_LOGIC_VECTOR type

WHILE NOT ENDFILE(fichier) LOOP

readline(fichier, ligne);
hread(ligne,data_int,good); -- Read the B argumen
WHILE good LOOP
WAIT UNTIL rising_edge(CLK_TS); -- pour synchroniser
DATA_TS <= data_int;
hread(ligne,data_int,good);
END LOOP;
END LOOP;

On DATA_TS output I'have the contain of the TS file .

What's happen ?

Is somebody can help me ?

Thanks a lot,
Etienne

Teten