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Synplify warnings

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I'm working with my first large scale VHDL project and have run into some
problems. I'm currently implementing a serial bus interface and getting a
bunch of warnings.

Warning number two below is repeated for all the bits of rx_vector and for
all bits of tx_buffer.


@W: CL112 :"C:\Actelprj\pwmtest\hdl\sb2.vhd":94:4:94:5|Feedb ack mux
created for signal rx_buffer[16:1]. Did you forget the set/reset
assignment for this signal?
@W: CL179 :"C:\Actelprj\pwmtest\hdl\sb2.vhd":101:4:101:5|Fou nd
combinational loop at rx_vector[15]

Should I worry about these warnings?
I have tried to sort them out but nothing seem to work...

If anything else seem weird please let me know

/Åke "Cazed" Forslund

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Cazed wrote:
> Source:

Now I have not much time to analyze the sourvce you have posted, but
anyhow, it is easy to see a first step to do:

You have a really long sensitivity list on all processes.

You should "always" limit any process to:

if reset='1' then
-- ......
elsif rising_edge(clock) then -- OK, let it be falling_edge(clock)
-- .....
end if;
end process;

Keep in mind that any desing will be created using mainly flip-flops
with asynchronous clear/preset inputs (thus the rese in the sensitivity
list), a cock input (yes, the one named in the sensitivity list), and
some data inputs (data, enable...) created by logic combination of other
signals and always SYNCHRONOUS as they are validates by clock edges.

Making every part of the design synchronous in some clock and with
asynchronous reset makes life easy for the VHDL compiler, for the
simulator and, above all, for /you/.

I supose that if you change your desing to observe these rukles, all
warnings will disappear. And you will find simulation and testing a
delightful experience (well, more or less )

Best regards
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