Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > How to print std_logic_vector variable into hex string in VHDL

Reply
Thread Tools

How to print std_logic_vector variable into hex string in VHDL

 
 
Carson
Guest
Posts: n/a
 
      08-31-2005
Hi,

How to print std_logic_vector variable into hex string in VHDL?

Thanks,

Carson

 
Reply With Quote
 
 
 
 
Niv
Guest
Posts: n/a
 
      08-31-2005

> How to print std_logic_vector variable into hex string in VHDL?
>


Forgotten the exact syntax & textbook not to hand, but something like:

use std.textio

and then use:

HWRITE (myline, signame);
WRITELINE (myfile, myline);
where signame is your std_log_vec.

Niv.


 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      08-31-2005
Carson wrote:

> How to print std_logic_vector variable into hex string in VHDL?


Here's one way:
http://home.comcast.net/~mike_treseler/print_vec.vhd

-- Mike Treseler
 
Reply With Quote
 
Carson
Guest
Posts: n/a
 
      08-31-2005
Thanks,

Is there any command like "report integer'image(myvalue)"; so that it
will print out hex?

 
Reply With Quote
 
David Bishop
Guest
Posts: n/a
 
      09-01-2005
Mike Treseler wrote:
> Carson wrote:
>
>> How to print std_logic_vector variable into hex string in VHDL?

>
>
> Here's one way:
> http://home.comcast.net/~mike_treseler/print_vec.vhd


Here's another:

http://www.eda.org/vhdl-200x/vhdl-20..._additions.vhd

The function is called "to_hstring", it works like this:

report "The string was " & to_hstring (slvec)

There is also a "to_string" and "to_ostring" function in this package,
which containts all of the additions we plan to make to std_logic_1164
in VHDL-2006.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
std_logic_vector to string in hex format Mad I.D. VHDL 6 09-16-2009 04:58 AM
inout std_logic_vector to array of std_logic_vector of generic length conversion... Thomas Rouam VHDL 6 11-09-2007 11:49 AM
Hex Color Codes - Hex 6 <=> Hex 3 lucanos@gmail.com HTML 10 08-18-2005 11:21 PM
HEX to STD_LOGIC_VECTOR ALuPin@web.de VHDL 2 06-06-2005 02:11 AM
hex(-5) => Futurewarning: ugh, can't we have a better hex than '-'[:n<0]+hex(abs(n)) ?? Bengt Richter Python 6 08-19-2003 07:33 AM



Advertisments