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Hi,

I would like to convert an algorithm that uses floating point ('real' and it's
subtypes defined by me) into a fixed point version so that the design that
uses the algorithm can be synthesize-able (the synopsys tool I am going to use
cannot synthesize 'real' and it seems no tools can do this yet).

First, I plan to make a package for a type based on std_ulogic_vector which
will store the unsigned versions of the whole and fractional part of the
corresponding 'real'. Are there already packages out there to for this type
of conversion or should I continue writing my own? If the latter, is this the
right approach/what are alternate approaches?

I will appreciate any pointers.

wrote:
> Hi,
>
> I would like to convert an algorithm that uses floating point ('real' and it's
> subtypes defined by me) into a fixed point version so that the design that
> uses the algorithm can be synthesize-able (the synopsys tool I am going to use
> cannot synthesize 'real' and it seems no tools can do this yet).
>
> First, I plan to make a package for a type based on std_ulogic_vector which
> will store the unsigned versions of the whole and fractional part of the
> corresponding 'real'. Are there already packages out there to for this type
> of conversion or should I continue writing my own? If the latter, is this the
> right approach/what are alternate approaches?
>
> I will appreciate any pointers.

you will find synthesizable packages for fixed and floating point at:
http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html

I've had some success with Synopsys. You may need to tweek a few functions.

David Bishop wrote:
> wrote:
>
>> Hi,
>>
>> I would like to convert an algorithm that uses floating point ('real'
>> and it's subtypes defined by me) into a fixed point version so that
>> the design that uses the algorithm can be synthesize-able (the
>> synopsys tool I am going to use cannot synthesize 'real' and it seems
>> no tools can do this yet).
>>
>> First, I plan to make a package for a type based on std_ulogic_vector
>> which will store the unsigned versions of the whole and fractional
>> part of the corresponding 'real'. Are there already packages out there
>> to for this type of conversion or should I continue writing my own? If
>> the latter, is this the right approach/what are alternate approaches?
>>
>> I will appreciate any pointers.
>
>
> you will find synthesizable packages for fixed and floating point at:
> http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html
>
> I've had some success with Synopsys. You may need to tweek a few
> functions.

Thank you very much! About what time frame will the newest standard
(with these packages or related packages) be available?

I will be testing it out in the coming week, is there anywhere I
can/should send feedback?

David Bishop wrote:
> wrote:
>
>> Hi,
>>
>> I would like to convert an algorithm that uses floating point ('real'
>> and it's subtypes defined by me) into a fixed point version so that
>> the design that uses the algorithm can be synthesize-able (the
>> synopsys tool I am going to use cannot synthesize 'real' and it seems
>> no tools can do this yet).
>>
>> First, I plan to make a package for a type based on std_ulogic_vector
>> which will store the unsigned versions of the whole and fractional
>> part of the corresponding 'real'. Are there already packages out there
>> to for this type of conversion or should I continue writing my own? If
>> the latter, is this the right approach/what are alternate approaches?
>>
>> I will appreciate any pointers.
>
>
> you will find synthesizable packages for fixed and floating point at:
> http://www.eda.org/vhdl-200x/vhdl-20...ges/files.html
>
> I've had some success with Synopsys. You may need to tweek a few
> functions.

I get these errors using 'ncvhdl -v93' (05.40-s00 when compiling
fixed_pkg_c.vhd:

VALUE (VALUE'range) := (others => 'U');
|
ncvhdl_p: *W,WAGNOOT (fixed_pkg_c.vhd,5865|33): OTHERS choice not
allowed in this context [7.3.2.2].
VALUE (VALUE'range) := (others => 'U');
|
ncvhdl_p: *W,WAGNOOT (fixed_pkg_c.vhd,5912|33): OTHERS choice not
allowed in this context [7.3.2.2].

[more similar errors on lines with the same problem]

I corrected these by using "VALUE := ((VALUE'range)=>'U');" instead of
the offending line. I don't know if this is helpful for the pending VHDL
standard, or even the VHDL'93 standard (could be just this tool).

I got these errors when compiling fixed_synth.vhd:

variable in1min2 : sfixed (SFixed_high(in1reg3, '*', in2reg3) downto
|
ncvhdl_p: *E,ILSGRD (fixed_synth_custom.vhd,105|49): illegal reference
of a signal (IN1REG3) during static elaboration [12.3].
variable in1min2 : sfixed (SFixed_high(in1reg3, '*', in2reg3) downto
|
ncvhdl_p: *E,ILSGRD (fixed_synth_custom.vhd,105|63): illegal reference
of a signal (IN2REG3) during static elaboration [12.3].
SFixed_low(in1reg3, '*', in2reg3));
|
ncvhdl_p: *E,ILSGRD (fixed_synth_custom.vhd,106|4: illegal reference
of a signal (IN1REG3) during static elaboration [12.3].
SFixed_low(in1reg3, '*', in2reg3));
|
ncvhdl_p: *E,ILSGRD (fixed_synth_custom.vhd,106|62): illegal reference
of a signal (IN2REG3) during static elaboration [12.3].


It seems that it doesn't like using signals to define variables: perhaps
sfixed16 could be used to get the ranges instead?