Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > VHDL-200X Fixed Point Divider

Reply
Thread Tools

VHDL-200X Fixed Point Divider

 
 
Divyang M
Guest
Posts: n/a
 
      08-18-2005
Hi,

I was wondering if the VHDL-200X fixed point divider is synthesizable
(by Altera Quartus)?

If so, what is the expected performance (speed / area) and is it
possible to pipeline the function for greater speed?

Thanks,
Divyang M

 
Reply With Quote
 
 
 
 
David Bishop
Guest
Posts: n/a
 
      08-19-2005
Divyang M wrote:
> Hi,
>
> I was wondering if the VHDL-200X fixed point divider is synthesizable
> (by Altera Quartus)?
>
> If so, what is the expected performance (speed / area) and is it
> possible to pipeline the function for greater speed?


It depends. The fixed point divide uses a signed divide from
numeric_std. It works in Synplicity, but I don't know about quartus.

I just finished a Newton Raphson divide routine for fixed point that I
will post soon. That one takes about 8 multiplies.
 
Reply With Quote
 
 
 
 
Divyang M
Guest
Posts: n/a
 
      08-19-2005
Thanks David. I will look forward to the divide routine.

I still owe you the part of the code using the fixed_pkg that works
with Quartus 4.2 but not with Quartus 5.0 (from one of my earlier
posts). I will e-mail it as soon as I pack it into a user-friendly
fashion.

--Divyang M.

 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Share-Point-2010 ,Share-Point -2010 Training , Share-point-2010Hyderabad , Share-point-2010 Institute Saraswati lakki ASP .Net 0 01-06-2012 06:39 AM
32-Bit Fixed Point Divider Needed phuxua...@gmail.com VHDL 3 06-20-2007 01:36 AM
floating point divider john VHDL 4 03-13-2007 09:54 AM
MCU clock divider vs. VHDL divider Matt Clement VHDL 3 04-28-2006 01:24 PM
converting floating point to fixed point H aka N VHDL 15 03-02-2006 02:26 PM



Advertisments
 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57