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seq. waveform

 
 
csosz33@axelero.hu
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      08-16-2005
Hi,


Why disappears the transaction marked with (*) in the simulation? I
have got '0' (0-20ns) after running this.


----------------------------

library ieee;
use ieee.std_logic_1164.all;

entity test2_tb is
end test2_tb;

architecture TB_ARCHITECTURE of test2_tb is
signal a : std_logic;
signal b : std_logic;
signal c : std_logic;
begin
STIMULUS: process
begin
a <= '0';
wait for 0 ns;

a <= '1' after 2 ns; -- (*)
a <= '0' after 4 ns;
wait for 20 ns;

wait;
end process;
end TB_ARCHITECTURE;

---------------------------


When I change the STIMULUS process to this one:

STIMULUS: process
begin
a <= '0';
wait for 0 ns;

a <= '1' after 2 ns;
a <= '1' after 4 ns;
wait for 20 ns;

wait;
end process;


It seems all transaction executed. The waveform is '0' in (0-2ns) and
'1' after 2 ns.


Thanks for any help
Attila

 
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Andy Peters
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      08-16-2005
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> Why disappears the transaction marked with (*) in the simulation? I
> have got '0' (0-20ns) after running this.
> ----------------------------
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity test2_tb is
> end test2_tb;
>
> architecture TB_ARCHITECTURE of test2_tb is
> signal a : std_logic;
> signal b : std_logic;
> signal c : std_logic;
> begin
> STIMULUS: process
> begin
> a <= '0';
> wait for 0 ns;
>
> a <= '1' after 2 ns; -- (*)
> a <= '0' after 4 ns;
> wait for 20 ns;
>
> wait;
> end process;
> end TB_ARCHITECTURE;


Go read up on assignment scheduling.

After the "wait for 0 ns," you assign a twice. The problem is that you
don't allow the first assignment to occur before overwriting it with
the second.

-a

 
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csosz33@axelero.hu
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Posts: n/a
 
      08-18-2005
Ok, in but the second case I have got waveform starting at 2ns: '0' in
(0-2ns) and '1' after 2 ns. Why?

 
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Andy Peters
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Posts: n/a
 
      08-18-2005
(E-Mail Removed) wrote:

> Ok, in but the second case I have got waveform starting at 2ns: '0' in
> (0-2ns) and '1' after 2 ns. Why?
>
> STIMULUS: process
> begin
> a <= '0';
> wait for 0 ns;
> a <= '1' after 2 ns; -- (*)
> a <= '0' after 4 ns;
> wait for 20 ns;
> wait;
> end process;


> When I change the STIMULUS process to this one:
> STIMULUS: process
> begin
> a <= '0';
> wait for 0 ns;
> a <= '1' after 2 ns;
> a <= '1' after 4 ns;
> wait for 20 ns;
> wait;
> end process;


Why? Again, look up how transactions are scheduled. The quick answer
is: in the first process, the assignment

a <= '0' after 4 ns;

overrides the assignment:

a <= '1' after 2 ns;

Keywords: "inertial" and "transport."

-a

 
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csosz33@axelero.hu
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Posts: n/a
 
      08-20-2005
When I change the STIMULUS process to this one:

STIMULUS: process
begin
a <= '0';
wait for 0 ns;

a <= '1' after 2 ns;
a <= '1' after 4 ns;
wait for 20 ns;

wait;
end process;

It seems all transaction executed. The waveform is '0' in (0-2ns) and
'1' after 2 ns.

Why are this transactions (all) executed?

a <= '1' after 2 ns;
a <= '1' after 4 ns;

I tested it with Aldec 5.1 simulator.


Thanks for any help
Attila

 
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SUNNY
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      08-26-2005
Hi,
Since you have not specified the delay mechanism so the default delay
mechanism of intertial delay is used for driving signal a.With the
first assignement to a,transaction is scheduled on it and it is
executed when we reach the wait statement.Now when we reach the
statement
a <= something after 2 ns;
something is scheduled as a transaction on a in the signal driver,here
since you have not given the rejection limit so it is taken as the
delay of the first waveform element hence it is taken to be 2 ns.Now
when this transaction is added to the signal driver for signal a,there
is no other transaction in the signal driver hence nothing needs to be
deleted.Now when we reach the statement
a <= something after 4 ns;
another transaction is added to the signal driver for signal a which
already had a transaction scheduled which would have occured at 2ns.Now
when the above statement is executed since you have not specified the
rejection limit it is taken as the delay of the first waveform element
which in this case is 4 ns.So according to the rules of adding
transactions for intertial delay in case in the signal driver we have a
transaction at a space t(time for transaction) - trj(rejection time)
whose value is DIFFERENT then the value of the current transaction it
will be deleted from the the signal driver.So in case you specify both
values as 1 it works and in case you specify the values at those time
to be different the first assignment does not gets executed.

There are many ways to get the waveform that you are desiring,you could
use transport delay or you could use a rejection limit like 1 ns incase
your pulse rejection is like 1 ns.

 
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