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forcing 1,0 internal signal

 
 
Elinore
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      08-15-2005
Hi

In Xilinx XST document, I took 4bit counter example and modified it.

I am wondering this will work in read chip, while the simulation after
place and route, seems okay.



--4-bit unsigned up counter
--an asynchronous clear and a clock enable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
C, CLR, CE : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;

architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
signal clear: std_logic; -- modified
signal enable: std_logic; -- modified
begin

clear <= CLR; -- modified
enable <= CE; -- modified

clear <= '0'; -- modified : ground connect?
enable <= '1'; -- modified : VCC connect ?

process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
if (CE='1') then
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;

 
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Mike Treseler
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      08-15-2005
Elinore wrote:

> I am wondering this will work in read chip, while the simulation after
> place and route, seems okay.


If you expect it to no never CLR and always CE
then yes. It might be easier to just edit the
code:

process (C)
begin
if rising_edge(C) then
tmp <= tmp + 1;
end if;
end process;


-- Mike Treseler

 
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